Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-10-14
2004-09-07
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S700000, C438S701000, C438S702000
Reexamination Certificate
active
06787454
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, in particular, to a method of forming a dual damascene structure.
2. Description of the Background Art
In recent years, wiring structures of semiconductor devices have come to be formed by a dual damascene process in which a via hole (connection hole) and a trench (wiring trench) are formed integrally. As described in Japanese Patent Laid-Open No. 2002-203898, for example, a via-first method in which the via hole is formed before the trench has an advantage over a trench-first method that a sufficient opening margin is secured even if the trench is deviated from the via hole.
However, in the via-first method, to prevent a Cu interconnection from being damaged by trench formation etching, it is necessary to fill in the via hole with a filler material such as a resist or an organic ARC (anti-reflective coating) or the like in the following manner.
FIGS. 5A
to
5
G are sectional views showing a conventional method of manufacturing a semiconductor device.
First, as shown in
FIG. 5A
, an interlayer insulating film
2
is formed so as to cover a Cu interconnection
1
. Then, as shown in
FIG. 5B
, a via hole
3
is formed through the interlayer insulating film
2
by photolithography and etching. Then, as shown in
FIG. 5C
, a filler member
21
is formed on the interlayer insulating film
2
including inside the via hole
3
by spin coating or the like.
Subsequently, the filler member
21
is etched back as shown in
FIG. 5D. A
resist pattern
22
is thereafter formed on the interlayer insulating film
2
as shown in FIG.
5
E. Then, as shown in
FIG. 5F
, a trench
23
is formed by etching by using the resist pattern
22
as a mask.
Then, the resist pattern
22
and the filler member
21
are removed as shown in FIG.
5
G. Thereafter, a wiring material such as Cu or the like is buried in the trench
23
and the via hole
3
to form a wiring structure.
In the above conventional method in which the filler member
21
is formed by spin coating, the filler member
21
needs to be etched back.
However, it is difficult to accurately control a thickness of the filler member
21
in an etch-back step, raising a problem that a height of the filler member
21
varies within the substrate and a height of the trench formation resist
22
varies accordingly as shown in FIG.
6
A.
If photolithography is performed in such a state, differences occur between opening widths A of the resist pattern
22
as shown in
FIG. 6B
, as a result of which a dimension of a trench interconnection varies.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device.
A more specific object of the present invention is to increase a controllability of a dimension of a trench formation resist pattern.
The above object of the present invention is attained by a following method of manufacturing a semiconductor device.
According to an aspect of the present invention, in the method, a via hole, which reaches an underlying interconnection through an interlayer insulating film that covers the underlying interconnection, is first formed. Next, a conductive polymeric member is formed in the via hole by electrolysis. Then, a resist pattern is formed on the interlayer insulating film. Finally, a trench connected to the via hole is formed by etching by using the resist pattern as a mask.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5091339 (1992-02-01), Carey
patent: 5173442 (1992-12-01), Carey
patent: 5219787 (1993-06-01), Carey et al.
patent: 6607654 (2003-08-01), Lee et al.
patent: 2002/0036144 (2002-03-01), Lee et al.
patent: 2003/0116439 (2003-06-01), Seo et al.
patent: 2004/0007325 (2004-01-01), Pan et al.
patent: 2002-203898 (2002-07-01), None
Gurley Lynne
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
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