Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-05-02
2004-03-23
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C438S108000
Reexamination Certificate
active
06710446
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor devices as well as semiconductor modules; and, more particularly, the invention relates to architectures or techniques for fabricating semiconductor elements in a form capable of being mounted in units of wafers and for subdividing this into necessary sizes to thereby obtain the intended semiconductor devices.
In recent years, as electrical and electronic parts or components are increasing more and more in performance, semiconductor elements have likewise increased in integration density and functionality in a way such that the IC complexity has advanced from large-scale integration (LSI) to very-large-scale integration (VLSI), and finally to ultralarge-scale integration (ULSI). Such technological growth results in further increases in dimension and pin number, plus the operating rate of the elements involved. To accommodate this technical trend, package structures for use with multiple-pin semiconductor devices have been shifted from those having connection terminals at two opposite sides of a semiconductor element to others having connection terminals arrayed along four side edges thereof. Further, in order to meet the needs for multi-pin package schemes, so-called “grid array” structures have been developed and reduced to practice, which are designed to employ a multilayer carrier substrate for permitting required connection terminals to be laid out into a grid-like pattern on the entire area of a parts-mount surface. The grid-array structures typically include a ball grid array (BGA) structure that has presently been employed from time to time, which is arranged so that those terminals used therein are of a ball-like shape to thereby enable achievement of high-speed signal transmission and low inductance. In addition, to attain the high-speed signal transmissivity required, a multilayer carrier substrate made of chosen organic materials has been used, which materials are inherently lower in dielectricity than currently available inorganic materials. Unfortunately, the use of such organic materials resulted in many problems relating to the difficulty of attaining enhanced reliability due to the presence of risks of occurrence of electrical connection defects, including unwanted open-circuiting and/or short-circuiting, because of the fact that the organic materials are inherently greater in thermal expansion coefficient than standard silicon-based materials that have been often employed for semiconductor elements; and, for this reason, thermal stresses can take place due to possible differences in thermal expansion coefficient therebetween.
Moreover, from the view point of high-density mounting/packaging design schemes today, a need also exists for a semiconductor device of the chip scale package (CSP) structure type which is substantially the same in size as a semiconductor element associated therewith. One typical known approach to achieving this is to employ a specific structure that eliminates the use of any carrier substrate in the CSP with BGA structures. This is a mount structure permitting direct connection between a semiconductor element and its associated mount substrate or board, and one typical package structure incorporating this principle has been disclosed in U.S. Pat. No. 5,148,265, which is capable of improving the reliability of connector portions by making use of a chosen material that is low in modulus of elasticity to reduce or “relax” any possible stress forces occurring due to thermal expansion coefficient differences between the semiconductor element and its mount board. This package structure is designed so that the required electrical interconnection between the semiconductor element and the mount board is done by use of a lead tape made of an organic material such as polyimide or, in the alternative, of the carrier substrate. Due to this, wire-bonding techniques or other similar bonding methods using electrical leads are employed for electrical connection portions including external terminals of the semiconductor element and those conductive circuit sections of such lead tape. Additionally ball-like terminals made of solder or the like are used for connection between the lead tape and the mount board's conductive portions. The manufacture of this structure does require an increased number of new process steps including, but not limited to, the steps of disposing a low-elasticity material at the semiconductor element, connecting the lead tape, forming ball terminals, and then sealing electrical connection portions; accordingly, this approach requires a new manufacturing facility, while also requiring that the individual one of resultant semiconductor devices be assembled and mounted on a per-chip basis, which would result in association of many disadvantages as to the manufacturability when compared to prior art methods thereby causing the CSP structure's inherent advantages of high-density mountability to be less achievable during reduction to practice.
The present invention has been made in light of the technical background stated above to provide an improved semiconductor device manufacturing method which is low in cost and excellent in mass-productivity for enabling, through use of low-elasticity organic materials, a reduction or relaxation of thermal stresses occurring between a semiconductor element or elements of grid-array structure accommodatable to multi-pin design schemes and its associative mount substrate or board for fabrication into a specific form mountable in units of wafers, to thereby achieve subdivision into necessary sizes, along with a semiconductor device or module which is excellent in reliability of electrical connection and high-speed signal transmissivity plus multi-pin scheme accommodatability.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device which comprises a semiconductor element for formation of integrated circuitry, a plurality of electrode pads that formed on an integrated circuit formation surface side of the semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer that is formed between the integrated circuit formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand and is adhered thereto, wherein the semiconductor device is featured in that more than one third of the stress relaxation layer from a surface thereof is cut away for removal and in that the stress relaxation layer is divided into a plurality of regions.
The present invention may be applied to a semiconductor device having a plurality of pads formed in peripheral regions of the integrated circuit formation surface of a semiconductor element, one or several external electrodes electrically connected via a conductive layer to the pads, and a stress relaxation layer that is adhered to the integrated circuit formation surface and the pads plus the external electrodes as well as the conductive layer. The stress relaxation layer or stress buffering layer may be subdivided into a plurality of portions independently of one another. Optionally, a sealing resin may be provided which is in close contact with the stress relaxation layer. Where necessary, the sealing resin may come with division slits at appropriate positions for reduction of virtual modulus of elasticity to thereby suppress those stress forces being applied to the semiconductor element. More than one third of the stress relaxation material from its surface is cut away for removal, and this stress relaxation material may be divided in a way corresponding to each conductive layer.
The stress relaxation layer or stress buffer layer functions to make moderate or “soften” those thermal stresses that can take place due to possible differences in thermal expansion coefficient between the semiconductor elements and its associative mount substrate or board. Any one of the stress relaxation layer and buffer materials along w
Akahoshi Haruo
Anjoh Ichiro
Eguchi Syuji
Nagai Akira
Nishimura Asao
Antonelli Terry Stout & Kraus LLP
Cruz Lourdes
Cuneo Kamand
Renesas Technology Corporation
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