Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-13
2004-05-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S018000
Reexamination Certificate
active
06735744
ABSTRACT:
I.B. Field
This disclosure teaches novel techniques related to power estimation for circuits. Specifically, cycle-accurate power macro-modeling techniques for complex circuit components are taught. As a specific example, RTL circuits are discussed, though the techniques discussed are equally applicable for all kinds of circuits regardless of their representation.
I.C. Background
1. Introduction
Power dissipation is a mainstream design metric in deep sub-micron system-on-chip technologies. This is due to the signal integrity and power delivery concerns associated with deep sub-micron technologies. The increasing complexity of system chips has led to the adoption of high-level design methodologies in order to bridge the gap between design and productivity. High-level power estimation is critical to supporting power budgeting and tradeoffs when designing the system architecture.
The application of high-level power estimators ranges from simple tasks like relative comparison of alternative circuit designs with respect to their power dissipation, to sophisticated uses like chip-level power grid analysis and design, I-R drop calculation for static timing analysis, and hot-spot sensitive system floor-planning. This increasing importance of power estimation has significantly raised the requirements of the estimation accuracy. Many of the latter mentioned applications require absolute accuracy and cycle-by-cycle power estimates that can be correlated with functional and timing information related to the circuit.
2. References
The following papers provide useful background information, for which they are incorporated herein by reference in their entirety, and are selectively referred to in the remainder of this disclosure by their accompanying reference numbers in square brackets (i.e., [3] for the third numbered paper by J. Monteiro and S. Devdas):
[1] J. Rabaey and M. Pedram,
Low Power Design Methodologies
. Kluwer Academic Publishers, Norwell, Mass., 1996.
[2] A. R. Chandrakasan and R. W. Brodersen,
Low Power Digital CMOS Design
. Kluwer Academic Publishers, Norwell, Mass., 1994.
[3] J. Monteiro and S. Devdas,
Computer
-
Aided Design Techniques for Low Power Sequential Logic Circuits
. Kluwer Academic Publishers, Norwell, Mass., 1996.
[4] M. Pedram, “Power minimization in IC design: principles and applications,” in
ACM Trans. Design Automation Electronic Systems
, vol. 4, no. 1, pp. 3-56, January 1996.
[5] S. Powell and P. Chau, “Estimating power dissipation of VLSI signal processing chips: The PFA techniques,” in
Proc. IEEE Workshop on VLSI Signal Processing IV
, vol. IV, pp. 250-259, 1990.
[6] P. Landman and J. Rabaey, “Power estimation for high-level synthesis,” in
Proc. European Design Automation Conf.
, pp. 361-366, February 1993.
[7] D. Marculescu, R. Marculescu and M. Pedram, “Information theoretic measures for energy consumption at RTL,” in
Proc. Intl, Symp. Low Power Electronics
, pp. 81-86, April 1995.
[8] M. Nemani and F. Najm, “High-level power estimation and area complexity of Boolean applications,” in
Proc. Intl. Symp. Low Power Electronics
, pp. 329-334, August 1996.
[9] A. Raghunathan, S. Dey and N. K. Jha, “RTL estimation techniques for switching activity and power consumption:’ in
Proc. Intl Conf Computer
-
Aided Design
, pp. 583-588, November 1996.
[10] L. Benini, A. Bogliolo, M. Favalli, and G. DeMicheli, “Regression models for behavioral power estimation,” in
Proc. of Intl. Workshop—Power and Timing, Modeling, Optimization and Simulation,
1996.
[11] Q. Wu, C. Ding, C. Hsieh and M. Pedram, “Statistical design of macro-models for RT-level power estimation,” in
Proc. Asia and South Pacific Design Automation Conf.
, pp. 523-528, January 1997.
[12] Z. Chen, K. Roy and K. P. Chong, “Estimation of power sensitivity in sequential circuits with power macromodeling application:’ in Proc. Intl. Conf. Computer-Aided Design, pp. 468-472, 1998.
[13] S. M. Wiess and C. A. Kulikowski,
Computer Systems that Learn
. Morgan Kaufmann 1991.
[14] W. N. Venables and B. D. Ripley,
Modern Applied Statistics with S
-
PLUS
. Springer-Verlag 1998.
[15] W. N. Venables and B. D. Ripley, Modern Applied Statistics with S-PLUS. Springer-Verlag 1998.
[16] Open CAD V 5 Users Manual. NEC Electronics, Inc. 1997.
[17] CBC9VX Library Manual. NEC Electronics, Inc. 1997.
[18] CYBER Reference Manual. NEC Electronics, Inc. 1997.
3. Related Work
It is well known that power estimation is more accurate in lower-level power estimators, while it is more computationally efficient in higher-level power estimators. Transistor and gate-level power estimation techniques have been well researched [1, 2, 3, 4], and several commercial tools exist that are reasonably mature. While there has also been some research on high-level power estimation techniques [5, 6, 7, 8, 9, 10, 11, 12], their limited accuracy has been one of the major challenges facing their widespread adoption.
High-level power estimators can be classified on the basis of the information they produce (e.g., spatial and temporal resolution of the power report), as well as the techniques employed (e.g., fast synthesis based, analytical, macro-modeling based, etc.). Aggregate estimators are those which, when given a complete set of input vectors or sequences, report the average power dissipated in the circuit when the complete set of vectors are applied. Applications where power dissipation information needs to be correlated with functional or timing information (e.g., peak power constraints, transient hot-spot analysis, and “power debugging”), require power values on a cycle-by-cycle basis.
This disclosure is aimed at teaching a novel technique to address the problem of improving the accuracy of high-level power estimation. The disclosed technique is in the context of a cycle-accurate macro-modeling based power estimation methodology.
In a general sense, macro-modeling is a commonly used technique for high-level power estimation. Macro-modeling techniques formulate the power consumed (dependent variable), in terms of parameters (independent variables) that are easily observable at a high level of abstraction. Some examples of power macro-models are linear or non-linear equations and look-up tables.
The concept of cycle-accurate high-level macro-models was used in [10, 11]. A cycle-accurate macro-model gives the power dissipated in each cycle of operation. That is, given a set of vectors, a cycle-accurate macro-model gives the power dissipated by every vector pair applied to the circuit. If P
k
is the power consumed by a module in cycle k, it can be defined as
P
k
=F
(
V
k−1·
V
k
)
where, V
k−1
and V
k
represent the input vectors for the module at cycles k−1 and k respectively. Note that the above equation can be extended to account for the dependence of power consumption on any finite history of input values. In practice, the power dissipation of atomic RTL components (functional units, multiplexers/buses, and latches/registers) is amenable to being modeled by the above equation, and more complex blocks can be decomposed into these atomic components for power estimation. The function F is referred to as the macro-model. It is parameterized with respect to some variables, which can be derived from the input vector pair. The goal of power macro-modeling (or characterization) is to derive F itself. The inputs to the macro-modeling procedure are a set of characterization vectors and the corresponding cycle-by-cycle power consumption values (derived using an accurate lower-level power estimator on a gate- or transistor-level implementation). With minimal additional effort, cycle-accurate macro-models can also provide the average power dissipated (akin to the behavior of aggregate estimators).
This Application is related to co-pending U.S. application Ser. No. 09/771100, titled “Multi-Level Power
Chakradhar Srimat T.
Hsiao Michael S.
Lakshminarayana Ganesh
Potlapally Nachiketh
Raghunathan Anand
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