Semiconductor device including SOI substrate

Details Semiconductor device including SOI substrate Semiconductor device including SOI substrate

2002-08-22

2004-04-27

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S354000

Reexamination Certificate

active

06727553

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a SOI substrate and to a method for fabricating the same.
In recent years, rapid miniaturization in the field of semiconductor devices has spurred the trends toward higher-speed operation and lower power consumption. However, conventional processes using bulk silicon wafers are approaching their limits in terms of achieving higher-speed operation and lower power consumption. On the other hand, there have been growing expectations for processes using silicon-on-insulator (hereinafter referred to as SOI) wafers as next-generation devices.
In a process using a SOI device, such as a MOS transistor, formed on a SOI wafer, emphasis has been placed on compatibility with a process using bulk silicon.
FIGS. 15A and 15B
and
FIGS. 16A and 16B
are cross-sectional views illustrating the process steps of fabricating a conventional SOI device.
First, in the step shown in
FIG. 15A
, a buried oxide film layer (BOX layer)
101
is formed by a method of implanting oxygen ions into a region at a given depth from a surface of a semiconductor substrate
100
or the like. Then, a Si layer
102
is formed on the BOX layer
101
. After an oxide film
103
and a silicon nitride film
104
are grown on the Si layer
102
, the oxide film
103
and the silicon nitride film
104
are patterned by lithography and dry etching so that openings are formed in isolation regions
105
.
Next, in the step shown in
FIG. 15B
, the Si layer
102
is patterned by dry etching by using the silicon nitride film
104
as a mask so that transistor regions
102
a
each composed of the Si layer are formed, while trenches
106
are formed simultaneously in the isolation regions
105
.
Next, in the step shown in
FIG. 16A
, the side surfaces of the transistor region
102
a
are oxidized so that sidewall oxide films
107
are formed. At the same time as the formation of the sidewall oxide films
107
, the edge portions of the upper surfaces of the transistor regions
102
a
are rounded off so that the localization of an electric field to the edge portions is suppressed.
Then, in the step shown in
FIG. 16B
, CVD oxide films are buried in the trenches
106
to form buried shallow trench isolations
110
(hereinafter referred to as STIs).
However, the conventional SOI device has the following problems.
Since the transistor regions
102
a
each composed of the Si layer are isolated electrically completely by the BOX layer
101
and the STIs
110
on the SOI wafer, the body potential of each of the transistor regions
102
a
is difficult to fix. To fix the body potential, therefore, the conventional SOI device requires a special pattern using a layout different from the layout of a bulk silicon device.
In addition, the lower-surface edge portions of the transistor regions
102
a
in contact with the BOX layer
101
are significantly oxidized when the sidewall oxide films
107
are formed in the step shown in FIG.
16
A. At this time, the transistor regions
102
a
are oxidized not only by oxygen passing through the sidewall oxide films
107
being formed but also by oxygen passing through the BOX layer
101
, so that abnormal oxide regions
109
are formed. This warps the lower-surface edge regions of the transistor regions
102
a
upward and deforms the substrate. Consequently, a failure occurs in the portion of the transistor regions
102
a
on which the stress of deformation is exerted and malfunction or a leakage current resulting from the failure may occur.
However, if an amount of oxidation is reduced for the suppression of abnormal oxidation of the lower-surface edge regions of the transistor regions
102
a
as described above, the upper-surface edge portions of the transistor regions
102
a
cannot be rounded off satisfactorily. This causes the localization of an electric field to the upper-surface edge portions. In the subsequent step, the problem of a reduction in threshold voltage may occur due to partial destruction of a gate oxide film.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide a SOI device wherein a body potential can be fixed without using a special pattern and a method for fabricating the same.
A second object of the present invention is to provide a SOI device wherein the localization of an electric field is suppressed by oxidizing the upper-surface edge portions of a transistor region of a SOI substrate, while suppressing the oxidation of the lower-surface edge portions of the transistor region and thereby preventing the occurrence of a failure, and a method for fabricating the same.
A semiconductor device according to the present invention comprises: a substrate insulator layer provided on a semiconductor substrate; a plurality of semiconductor layers which are provided on the substrate insulator layer and formed with a semiconductor element; a trench laterally surrounding the semiconductor layers and having at least one portion thereof reaching the semiconductor substrate; and a sidewall composed of a conductor material, provided along side surfaces of the trench, and having at least one portion thereof extending from above a surface of the semiconductor layers via a surface of the substrate insulator layer to reach a surface of the semiconductor substrate.
In the arrangement, the sidewall extending from the semiconductor layers to the semiconductor substrate provides a connection between the semiconductor layers and an eternal circuit so that the body potential of the semiconductor element is fixed easily.
The semiconductor layers have a region to be formed with a first-conductivity-type transistor and a region to be formed with a second-conductivity-type transistor and a portion of the trench located between the region to be formed with a first-conductivity-type transistor and the region to be formed with a second-conductivity-type transistor is not reaching the semiconductor substrate. If an RF signal is used, the arrangement suppresses the occurrence of noise which is likely to occur when the respective active regions of the first-conductivity-type transistor and the second-conductivity-type transistor are in close proximity.
A top portion of the sidewall is at a level lower than the upper surface of the semiconductor layers. The arrangement allows supply of oxygen from above the upper-surface edge portions of the semiconductor layers when the upper-surface edge portions of the semiconductor layers are oxidized to be rounded off so that the edge portions are rounded off easily.
At least one portion of the substrate insulator layer having a specified thickness is interposed between the semiconductor substrate and a bottom surface of the portion of the trench located between the region to be formed with a first-conductivity-type transistor and the region to be formed with a second-conductivity-type transistor. The arrangement more positively suppresses noise which is likely to occur in the semiconductor deice when the respective active regions of the first-conductivity-type transistor and the second-conductivity-type transistor are in close proximity.
A bottom surface of the portion of the trench located between the region to be formed with a first-conductivity-type transistor and the region to be formed with a second-conductivity-type transistor may be at a level higher than a lower surface of the substrate insulator layer.
A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device using a substrate having a substrate insulator layer provided on a semiconductor substrate and a semiconductor layer for forming an active layer of a semiconductor element, the semiconductor layer being provided on the substrate insulator layer, the method comprising the steps of: (a) removing a portion of the semiconductor layer and a portion of the substrate insulator layer to form a trench laterally surrounding the semiconductor layer and having at least one portion thereof reaching the semiconductor substrate; a

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