Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2002-01-19
2004-01-06
Chambliss, Alonzo (Department: 2827)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S613000, C438S622000, C438S623000, C438S780000
Reexamination Certificate
active
06673698
ABSTRACT:
BACKGROUND OF INVENTION
(1) Technical Field
This invention relates in general to the interconnection and packaging of semiconductor dies and discrete components.
(2) Description of Prior Art
The following publications relate to the use of thin films in the interconnection and packaging of semiconductor dies.
Microelectronic Packaging Handbook Chapter 9. R. R. Tummala, E. J. Rymaszewski. Van Nostrand Reinhold 1989.
Novel Microelectronic Packaging Method For Reduced Thermomechanical Stresses on Low Dielectric Constant Materials R. M. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, G. J. Vandentop. Intel Corp. Chandler, Ariz.
The requirements for packaging of semiconductor circuit devices are that the package provides physical protection, thermal control, powering capability, and desirable electrical properties of the interconnections. Semiconductor packages also provide the physical translation of interconnecting wiring structures from the fine wiring and wire spacing, and small area, of the semiconductor chip to the bigger interconnection spacing and larger area of the next level of assembly. This capability is usually referred to as “fan-out”. In addition the packages need to provide the ability to integrate passive components, such as capacitors, inductors, resistors, waveguides, filters, MEMS (MicroElectroMechanical) devices, and the like, into the wiring structure.
These demands have been and are currently met by numerous package designs. In general these designs tend to degrade the signals that communicate between devices. Usually this degradation is due to the high dielectric constant materials and high resistance metal used as insulators in the interconnection design. The materials used as insulators; silicon oxides, glass, glass ceramics, or ceramics are chosen for their mechanical properties and the method of fabrication. An important mechanical property is the material's thermal coefficient of expansion, or TCE. The TCE in many package designs needs to match that of the silicon semiconductor die in order to have low mechanical stresses in the package structure.
Materials with low TCE also have high dielectric constants (k). The high dielectric constants result in unwanted electrical properties of the interconnections; i.e., high impedances. Examples of such designs are semiconductor packages that utilize ceramic substrates to mount and interconnect the semiconductor circuits.
In order to take advantage of the high switching speeds of today's digital circuits the interconnection technology both on and off the semiconductor chips or dies requires novel approaches utilizing low dielectric constant (k) materials such as polyimide or BCB (benzocyclobutene) to provide the necessary electrical parameters of the interconnects that do not degrade circuit performance.
The use of low dielectric materials used as insulating layers for interconnects also requires novel mechanical design approaches to minimize the deleterious effects of TCE mismatches.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a semiconductor interconnecting package design and method of fabrication utilizing polymer thin film techniques.
It is a farther objective of the invention that the semiconductor package provide the interconnect density required by the semiconductor design.
It is also the objective of the present invention to provide a semiconductor package that allows for input and output interconnections on a pitch compatible both with the semiconductor and the next level of package.
The capability to place discrete components close to the semiconductor circuit's input and output connections is an additional objective of the present invention.
In addition an objective of the present invention is to utilize current fabrication techniques and existing fabrication infrastructure.
The above objectives are achieved by the present invention by utilizing a glass or glass-metal composite substrate as the basic structure of the package. Semiconductor dies are bonded to the substrates and a thin film structure is fabricated utilizing metal and polymer films to interconnect the semiconductor dies. The glass or glass-metal composite substrate provides the necessary mechanical protection and support to the semiconductor dies. It also provides the planarity necessary for the fabrication of the interconnect polymer layers that interconnect the semiconductors.
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Microelectronic Packaging Handbook, Chapter 9, R.R. Tummala et al., Van Nostrand Reinhold, NY, 1989, pp. 673-725.
Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials, R.M. Emery, et al., Intel Corp., Chandler, AZ.
Huang Ching-Cheng
Lee Jin-Yuan
Lin Mou-Shiung
Ackerman Stephen B.
Chambliss Alonzo
Megic Corporation
Saile George O.
Schnabel Douglas R.
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