Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2002-10-17
2004-03-16
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
06707315
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to user programmable logic devices. More particularly, the invention relates to a macrocell in which product terms can be allocated between an OR gate and registered logic, and in which product terms can be summed together with product terms from an adjacent macrocell.
User programmable logic devices provide flexibility in digital logic design by allowing a designer to implement logic functions through a sum-of-products architecture typically composed of an array of AND gates connected to an array of OR gates. The outputs from the AND gates are referred to as product terms. The output of each OR gate provides the sum of the input product terms.
Typically, a macrocell receives a number of product terms as inputs. Some of the product terms are input to the OR gate. The output of the OR gate then is typically fed to a register which stores the result. Some devices feature additional combinatorial logic associated with the register (registered logic). This logic typically allows inputs to the register to be inverted or combined with the output of the register or with the product terms not used by the OR gate.
In a typical macrocell, the number of product terms that can be ORed together is limited to the number of product terms that are input to the macrocell. Another type of conventional macrocell has the ability to share its OR function with a second macrocell, but in such a macrocell use of the OR function by the second macrocell precludes use of the remaining logic in the macrocell. Also, in a conventional macrocell having the ability to steer product terms to either an OR gate or to registered logic, use of the OR function must be sacrificed when product terms are steered to the registered logic.
In view of the foregoing, it is an object of this invention to provide a macrocell which supports summing of an arbitrary number of product terms by daisy chaining the OR gates of an arbitrary number of macrocells. It is a further object of this invention to provide a macrocell in which use of its OR function by another macrocell does not prevent the use of the remaining logic elements of the macrocell. It is another object of this invention to provide a macrocell in which product terms may be steered to the register logic without sacrificing use of the OR function.
The following are hereby incorporated by reference herein in their entireties: U.S. patent application Ser. No. 09/677,156, filed Oct. 2, 2000 (of which this is a continuation), now U.S. Pat. No. 6,366,119, and Pedersen U.S. Pat. No. 5,598,108 (also incorporated by reference in application Ser. No. 09/677,156).
SUMMARY OF THE INVENTION
This invention provides a macrocell with product term allocation and adjacent product term stealing. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms input to the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. By the process of adjacent product term stealing, product terms are allocated between macrocells. Because the programmable configuration switches can direct individual input product terms to the secondary inputs to the register instead of the OR gate, the register and register accompanying logic can be used even when an adjacent macrocell steals the OR gate. The register and register accompanying logic provide output control for the macrocell. In one preferred embodiment, an EXCLUSIVE-OR gate with a plurality of selectable inputs allows the register to be implemented as a D or a T flip-flop.
REFERENCES:
patent: 4415818 (1983-11-01), Ogawa et al.
patent: 4742252 (1988-05-01), Agrawal
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4763020 (1988-08-01), Takata et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4789951 (1988-12-01), Birkner et al.
patent: 4864161 (1989-09-01), Norman et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4878200 (1989-10-01), Asghar et al.
patent: 4879481 (1989-11-01), Pathak et al.
patent: 4894563 (1990-01-01), Gudger
patent: 4903223 (1990-02-01), Norman et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 4918641 (1990-04-01), Jigour et al.
patent: 4931671 (1990-06-01), Agrawal
patent: 4942319 (1990-07-01), Pickett et al.
patent: 4963768 (1990-10-01), Agrawal et al.
patent: 4967107 (1990-10-01), Kaplinsky
patent: 4983959 (1991-01-01), Breuninger
patent: 5003202 (1991-03-01), Keida
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 5023484 (1991-06-01), Pathak et al.
patent: 5023606 (1991-06-01), Kaplinsky
patent: 5027011 (1991-06-01), Steele
patent: 5027315 (1991-06-01), Agrawal et al.
patent: 5053646 (1991-10-01), Higuchi et al.
patent: 5079451 (1992-01-01), Gudger et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5168177 (1992-12-01), Shankhar et al.
patent: 5191243 (1993-03-01), Shen et al.
patent: 5220214 (1993-06-01), Pedersen
patent: 5231312 (1993-07-01), Gongwer et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5350954 (1994-09-01), Patel
patent: 5414376 (1995-05-01), Hawes
patent: 5450608 (1995-09-01), Steele
patent: 5457409 (1995-10-01), Agrawal et al.
patent: 5598108 (1997-01-01), Pedersen
patent: 5821774 (1998-10-01), Veytsman et al.
patent: 5861760 (1999-01-01), Pedersen et al.
patent: 6157208 (2000-12-01), Pedersen et al.
patent: 6366119 (2002-04-01), Pedersen et al.
Bursky, D., “Shorter Delays, Heighten Small PLD Value,”Electronic Design, vol. 37, No. 3, Feb. 1989, pp. 49-58.
Agrawal, O.P., et al., “AMD's MACH Family Breaks PLD Speed and Density Barrier”, Wesson Conference Record, vol. 34, Nov. 1990, pp. 328-334.
Altera Max Family Architecture Product Information Bulletin 4, Altera Coporation, Jan. 1990, pp. 1-5.
Altera Max EPLD Family Device and Software Overview Data Sheet, Altera Coporation, Jan. 1990, pp. 23-81.
MACH Device Family High-Density EE CMOS Programmable Logic Data Sheet, Advanced Micro Devices, Inc., Oct. 1990, pp. 1-7, 14, 15, 28, 29.
MACH 3 and 4 Family Data Book, Advanced Micro Devices, Inc., 1993.
Plus Logic FPGA2020 Data Sheet, Plus Logic, Inc., date unknown, pp. 1-7.
Altera Corporation
Fish & Neave
Jackson Robert R.
Le Don
Lin Hong S.
LandOfFree
Registered logic macrocell with product term allocation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Registered logic macrocell with product term allocation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Registered logic macrocell with product term allocation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3217649