Delay locked loop design with diode for loop filter...

Details Delay locked loop design with diode for loop filter... Delay locked loop design with diode for loop filter...

2002-07-19

2004-04-27

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S538000, C375S376000, C331SDIG002

Reexamination Certificate

active

06727737

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
has, among other components, a microprocessor
12
, one or more forms of memory
14
, integrated circuits
16
having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths
19
, e.g., wires, buses, etc., to accomplish the various tasks of the computer system
10
.
In order to properly accomplish such tasks, the computer system
10
relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator
18
generates a system clock signal (referred to and known in the art as “reference clock” and shown in
FIG. 1
as sys_clk) to various parts of the computer system
10
. Modem microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor
12
and the other components of the computer system
10
use a proper and accurate reference of time.
Accordingly, as the frequencies of modem computers continue to increase, the need to rapidly transmit data between circuit interfaces also increases. To accurately receive data, a clock signal is often transmitted to help recover data transmitted to a receiving circuit by some transmitting circuit. The clock signal determines when the data should be sampled by the receiving circuit. Typically, the receiving circuit operates better when the clock signal is detected during the middle of the time the data is valid. To this end, a delay locked loop (“DLL”) is commonly used to generate a copy of the clock signal at a fixed phase shift with respect to the original clock signal.
FIG. 2
shows a portion of a typical computer system in which a DLL
30
is used. In
FIG. 2
, data
32
is transmitted from a transmitting circuit
34
to a receiving circuit
36
. To aid in the recovery of the data
32
by the receiving circuit
36
, a clock signal
38
is transmitted along with the data
32
. To ensure that the data
32
is properly latched by the receiving circuit
36
, the DLL
30
(which in
FIG. 2
is shown as being part of the receiving circuit
36
) regenerates the clock signal
38
to a valid voltage level and creates a phase shifted version of the clock signal
38
. Accordingly, the use of the DLL
30
in this fashion ensures (1) that the data
32
is properly latched by triggering the receiving circuit
36
at a point in time in which the data
32
is valid.
FIG. 3
shows a configuration of a typical DLL
40
. The DLL
40
uses a voltage-controlled delay line
42
, composed of several delay elements
43
, to delay an output clock signal, clk_out
45
, with a fixed phase shift relative to an input clock signal, clk_in
44
. A delay of the voltage-controlled delay line
42
is controlled by a feedback system including a phase detector
46
, a charge pump
47
, and a bias generator
48
. The phase detector
46
detects any phase offset (i.e., phase difference) between the input clock signal
44
and the output clock signal
45
and then accordingly generates pulses on UP
49
and DOWN
51
signals that control the charge pump
47
. Depending on the UP
49
and DOWN
51
pulses, the charge pump
47
transfers charge to or from a loop filter capacitor
53
via a control voltage signal, Vctrl
55
. The bias generator
48
receives the control voltage signal
55
and produces bias voltages Vbn
57
and Vbp
59
that adjust the delay of the delay elements
43
in the voltage-controlled delay line
42
. The DLL
40
is arranged such that the delay of the voltage-controlled delay line
42
attempts to maintain 180 degree phase shift between the input clock signal
44
and the output clock signal
45
. For a more detailed background on the operation and behavior of a DLL, see J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, November 1996.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a phase detector arranged to detect a phase difference between a first clock signal and a second clock signal; a charge pump arranged to output a control voltage signal dependent on the phase difference; a capacitor operatively connected to the control voltage signal; a diode operatively connected to the capacitor; and a voltage-controlled delay line arranged to receive the first clock signal and output the second clock signal dependent on the control voltage signal.
According to another aspect, an integrated circuit comprises means for detecting a phase difference between a first clock signal and a second clock signal, means for generating a signal dependent on the phase difference, means for storing charge to maintain a voltage potential on the signal, a diode arranged to control a leakage current of the means for storing charge, and means for delaying the first clock signal in order to generate the second clock signal, where the means for delaying is dependent on the signal.
According to another aspect, a method for performing a delay locked loop operation comprises comparing a phase difference between a first clock signal and a second clock signal, generating a control voltage signal dependent on the comparing, storing charge dependent on the control voltage signal using a capacitor, controlling a leakage current of the capacitor with a diode positioned in series with the capacitor, and delaying the first clock signal to generate the second clock signal dependent on the control voltage signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5334952 (1994-08-01), Maddy et al.
patent: 5523724 (1996-06-01), Assar et al.
patent: 5659588 (1997-08-01), Fiedler
patent: 5717353 (1998-02-01), Fujimoto
patent: 6275079 (2001-08-01), Park
patent: 6420914 (2002-07-01), Hasegawa
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.

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