Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-05-13
2004-05-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06737700
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a memory cell structure. More specifically, the present invention relates to a non-volatile memory cell structure and a manufacturing method thereof.
2. Description of the Prior Art
Computer storage media technology is evolving rapidly. While hard drives and CD-ROMs will still be around for years to come because of their high capacity and low cost, new forms of storage are constantly being developed. One technology that appears to have distinct advantages over conventional forms of storage is flash memory. Like conventional storage systems, flash memory is nonvolatile, requiring no power to maintain the stored information, and rewriteable.
FIG. 1
is a sectional schematic diagram illustrating a prior art non-volatile memory cell structure
1
. As shown in
FIG. 1
, prior art non-volatile memory cell structures
1
includes a substrate
10
, a tunneling oxide layer
11
formed on the substrate
10
, a floating gate formed on the tunneling oxide layer
11
, a dielectric layer
13
, and a control gate
14
. A drain region
15
and a source region
16
are provided in the substrate
10
.
FIG. 2
illustrates another prior art non-volatile memory cell structure
2
having a split gate for improving work performance and reliability of the non-volatile memory cell structure
2
. As shown in
FIG. 2
, the prior art non-volatile memory cell structure
2
includes a substrate
20
, a tunneling oxide layer
21
, a floating gate
22
, a dielectric layer
23
, a control gate
24
, a polysilicon spacer
25
, and an erase oxide layer
26
. A drain region
27
and a source region
28
are provided in the substrate
20
. The polysilicon spacer
25
functions as a split gate which is isolated from the substrate
20
and the stacked gate structure consisting of the floating gate
22
and the control gate
24
by the erase oxide layer
26
.
The manufacturing process for the above-mentioned prior art non-volatile memory cell structure
2
is complex. To manufacture the prior art non-volatile memory cell structure
2
as set forth in
FIG. 2
, a first polysilicon layer is deposited over the substrate
10
, which is thereafter patterned and etched to form the floating gate
22
. After this, a second polysilicon layer is deposited and is then patterned and etched to form the control gate
24
. After the formation of the control gate
24
, a third polysilicon layer is deposited thereon. The third polysilicon layer is subjected to an etching back process to form the split gate structure
25
. Therefore, it needs three polysilicon layers to complete the prior art non-volatile memory cell structure
2
.
However, the above-mentioned prior art non-volatile memory cell structure is quite not compatible with the manufacturing process for the peripheral logic circuit. It is well known that, in most cases, the peripheral logic circuit includes CMOS single-poly transistors. The memory cell structure determines the degree of integration between the manufacturing process for the non-volatile memory cells and the manufacturing process for the peripheral logic circuit thereof. Moreover, the coupling ratio of the above-mentioned prior art non-volatile memory cell structure is still low. It is known that the coupling ratio is basically proportional to the overlapping area between the floating gate and the control gate and is an important factor related to the operation of the non-volatile memory. Therefore, to maintain sufficient overlapping area between the floating gate and the control gate, namely, coupling ratio, the possibility of further miniaturizing the memory cell size is hindered.
In light of the foregoing, there is a need to provide an improved non-volatile memory cell structure that is capable of eliminating the aforementioned problems.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide an improved non-volatile memory cell structure having reduced numbers of polysilicon layer and increased overlapping area between control gate and floating gates.
Another object of the present invention is to provide a non-volatile memory cell structure having the control gate disposed between two floating gates, and the control gate and split gates are formed in the same etching step.
To achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described herein, the present invention provides a non-volatile memory cell structure including a substrate having thereon at least a drain and two sources. The drain is disposed between the two sources. A tunneling oxide layer is formed on the substrate. Two floating gates are disposed on the tunneling oxide layer, and each of the two floating gates is disposed between the drain and one of the two sources. A dielectric layer is disposed on the floating gates. A plurality of spacers are formed on sidewalls of the floating gates. A control gate is formed over the drain and is disposed between the two floating gates. Two split gates are symmetrically formed on an outer side of the floating gates opposite to the control gate.
According to one aspect of the present invention, the present invention also pertains to a manufacturing method for making the non-volatile memory cell structure. The manufacturing method includes the steps of providing a substrate having thereon a tunneling oxide layer, a floating gate layer and a dielectric layer;etching the floating gate layer and the dielectric layer in order to define two floating gates;forming a plurality of spacers on sidewalls of the floating gates;oxidizing the substrate to grow a control gate oxide layer between the two floating gates and split gate oxide layer on an outer side of each of the two floating gates; implanting ions into the substrate to form a drain between the two floating gates; depositing a gate layer over the substrate, the gate layer covering the dielectric layer and the spacers:forming a photo mask on the gate layer, the photo mask being disposed over the drain; and etching the gate layer to form a control gate over the drain and simultaneously form a split gate at the outer side of each of the two floating gate in a self-aligned manner, the split gate being opposite to the control gate.
It is advantageous to use the present invention because the control gate of the non-volatile memory cell is located between two floating gates, thereby increasing the overlapping area between the control gate and the floating gates. The overlapping area includes the sidewalls of the floating gates and a portion of the top surface of the floating gates. This results in an increased coupling ratio. Furthermore, the split gates and the control gate are formed by etching the same polysilicon layer (second polysilicon layer). Only two layers of polysilicon are needed to complete the non-volatile memory cell of this invention. By doing this, the manufacturing process for the novel non-volatile memory cell structure of this invention can be well compatible with the manufacturing process for the peripheral circuit.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5910912 (1999-06-01), Hsu et al.
patent: 6620683 (2003-09-01), Lin et al.
patent: 2003/0155599 (2003-08-01), Hsu et al.
Chang Ko-Hsing
Hsu Cheng-Yuan
Hsu Winston
Nelms David
Nguyen Thinh T
Powerchip Semiconductor Corp.
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