Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-12-27

2004-01-06

Fahmy, Jr., Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06674112

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device and, more particularly, to techniques adapted advantageously to a dynamic random access memory (RAM) or a semiconductor integrated circuit device incorporating such a memory.
BACKGROUND OF THE INVENTION
There exist dynamic RAMs with voltage generation circuits that use an internal charge pump circuit to boost a back bias voltage fed to a substrate and a selected voltage on word lines. One such dynamic RAM is disclosed illustratively in Japanese Published Unexamined Patent Application No. Hei 3-214699.
As is well known, a dynamic memory cell is made up of an address selection MOSFET and a data storage capacitor. A data item is stored according to whether the capacitor is charged or not charged. As the storage capacity is raised, the number of memory cells to be refreshed per refresh operation increases. This can hinder word lines from getting driven by an internal voltage boosted by the charge pump circuit. To further enhance the storage capacity thus requires prolonging the period of time in which data are held in memory cells and reducing the number of memory cells selected per refresh operation. Meeting such requirements would alleviate the load of the internal voltage in effect when word lines are selected for refresh operations.
A capacitor that holds data is discharged by means of two currents: a sub threshold leakage current flowing through a source-drain path of the address selection MOSFET in an off-state; and a PN junction leakage current flowing between the source and drain connected to storage nodes of the capacitor on the one hand, and a substrate or a well in which the source and drain are formed on the other hand. In a dynamic RAM of the above-mentioned type, a back bias voltage is supplied to the substrate for two purposes: to reduce the sub threshold leakage current by raising a threshold voltage of each address selection MOSFET, and to lower the parasitic capacity of a source and a drain diffusion layer connected to the bit line side.
In the dynamic RAM described above, the maximum allowable field intensity of a gate insulating film has been dropping recently as elements are getting smaller than ever. The conventional idea of simply raising the threshold voltage of the address selection MOSFET for a full-write operation in the memory cell above is no longer tenable, as the inventors of this invention have found. That is, suppose that an operating voltage (High level on bit lines) lowered to about 2.5 V is desired to allow for an increase of the selected level of a word line by as much as the raised threshold voltage in order to perform a full-write operation on the memory cell in question. In that case, the threshold voltage of the address selection MOSFET is illustratively as high as 1.5 V. This means that raising the threshold value to get a boosted voltage of about 4 V for the selection of a word line would exhaust necessary margins for the maximum allowable field-intensity in effect.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device that incorporates a dynamic RAM comprising smaller elements and offering longer data holding times than before. Another object of the invention is to provide a semiconductor integrated circuit device including a dynamic RAM which is simpler to process and which comprises smaller elements while offering longer data hold times than ever before. Other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings.
DISCLOSURE OF INVENTION
The invention envisages a semiconductor integrated circuit device wherein a positive bias voltage higher than a ground potential of the circuit is generated and supplied as a bias voltage to P-type well regions in which are formed address selection MOSFETs of dynamic memory cells.


REFERENCES:
patent: 5617369 (1997-04-01), Tomishima et al.
patent: 5970003 (1999-10-01), Miyatake et al.
patent: 6333873 (2001-12-01), Kumanoya et al.

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