Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-01
2004-01-13
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06678879
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for the design of integrated circuits generally and, more particularly, to a method and/or architecture for the automated design of integrated circuits.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an example of a conventional design system
10
is shown. The system
10
generally comprises a database design block
12
, a design rules block
14
, a verification tool block
16
and a mask data block
18
. Conventional approaches for the design of integrated circuits have relied on the use of design verification tools provided by vendors such as Cadence, Mentor Graphics, Avant!, etc. A designer produces a design for the integrated circuitry in a language recognizable by the design verification tool
16
. The design verification tool
16
is run according to certain design rules. The design rules are typically process technology dependent. The output of the tool verification block
16
is the mask data
18
that conforms to the applicable design rules for a given technology.
Unfortunately, before the designer is able to submit the design database to the verification tool block
16
, corrections to the design to account for various photolithographic effects and/or process effects must be made. For example, the proximity of features as laid out affects the sizing of those features. For instance, polysilicon lines (e.g., for gate structures, etc.) may “grow” or “shrink” when actually laid out, due primarily to the proximity of other nearby features/lines. Also, serifs may ensure that line/feature lengths are not exceeded when the lines/features are laid out. Corrections must be made for such effects.
Accordingly, in the past designers modified the “as drawn” designs to account for differential sizing and other effects. Some vendors, such as Microunity Systems Engineering, provided post-processing tools that allowed for the introduction of serif structures following the design rule verification step. However, such tools often require significant memory storage capabilities and significant processing time (e.g., on the order of several days to complete).
In addition, certain processing steps, such as chemical-mechanical polishing (CMP), affect the various areas of ICs differently, depending on the density of underlying features. In particular, CMP tends to erode the portions of the dielectric disposed over areas with less feature density to a greater extent than the portions of the dielectric disposed over areas of higher feature density. As a result, non-uniform wafer surfaces may be produced by the polishing processes. The non-uniform wafer surfaces can be corrected by the insertion of “dummy features” in areas of the IC (particularly the periphery) where fewer active features are located. Some approaches to inserting dummy features to date have included:
(1) designers laying out the dummy features themselves (i.e., designing in the dummy features), or
(2) painting dummy features over the entire IC layout and having the design verification tool remove any unwanted dummy features (leading to increased processing time and additional memory storage).
SUMMARY OF THE INVENTION
The present invention concerns a design tool, comprising a pattern injection tool configured to automatically allow for the inclusion of dummy structures, differential feature sizing and/or serif addition into integrated circuit (IC) designs, in a pre-processing stage.
The objects, features and advantages of the present invention include providing a method and/or architecture for automated design of integrated circuits (IC) that may (i) provide an automated design process for ICs, (ii) provide automatic implementation of formats suitable for fabrication, (iii) provide automatic implementation of dummy structures, differential sizing and/or serif addition, (iv) provide hierarchical pattern injection, (v) allow a designer to draw circuitry as desired at a design stage, (vi) reduce memory requirements, (vii) reduce processing time, and/or (viii) reduce or eliminate post processing techniques.
REFERENCES:
patent: 5923563 (1999-07-01), Lavin et al.
patent: 6237133 (2001-05-01), Suzuki
patent: 6249904 (2001-06-01), Cobb
patent: 6370679 (2002-04-01), Chang et al.
Bell Risto D.
Brooks Jarrod V.
Hawse Alan R.
Merchant James D.
Nikolic Dragomir
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Garbowski Leigh M.
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