Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-06-15
2004-04-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C375S257000, C375S258000, C333S117000, C333S120000
Reexamination Certificate
active
06724219
ABSTRACT:
FIELD OF THE INVENTION
Me present invention relates to broadband communications and digital subscriber line (DSL) technologies. More particularly, the present invention relates to amplifiers and line drivers employing active termination to synthesize the output impedance.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a traditional line interface
10
including a line driver amplifier
12
, a hybrid circuit
14
, and a transformer
16
. The transformer
16
has a turns ratio of 1:n, and couples a transmit signal (TX) from the line driver amplifier
12
to the transmission line
18
having a load impedance Z (typically Z=100&OHgr;). A matching resistor (often referred to as a back termination resistor R
bt
) is usually required between the amplifier
12
and the transformer
16
to implement a full duplex transmission and hybrid rejection. The value of the back termination resistor R
bt
is selected to match the line impedance R
L
seen by the amplifier
12
, and each of the back termination resistors R
bt
has a value of R
L
/2 for a differential structure as shown in FIG.
1
.
Although the back termination resistors Rub are necessary in order to properly terminate the receive signal and also to detect receive signal developed across the resistors, they waste one half of the power provided by the line driver amplifier
12
. Therefore, the signal swing V
A
output from the amplifier
12
is twice as large as the signal swing V
B
supplied to the transformer
16
. That is, the same amount of power as that is required to the transmission line
18
is dissipated at the matching resistors R
bt
.
The purpose of active termination or synthesizing impedance is to reduce the power dissipation of the amplifier in the back termination resistors.
FIG. 2
illustrates one scheme
20
to implement active termination to synthesize the output impedance of the amplifier, which simulates the back termination resistor within the amplifier itself. As shown in
FIG. 2
, an output amplifier
22
has two output stages
24
and
26
, and an internal resistor
28
(having a resistance R
int
) coupled between the two stages. The first output stage
24
includes a first output transistor, such as a metal oxide semiconductor field effect transistor (MOSFEI) M
1
, and is coupled to a node
23
. Similarly, the second output stage
26
includes a second output transistor M
2
, and is coupled to an output node
25
. The device ratio of the first transistor M
1
and the second transistor M
2
is 1:N.
The output impedance Z
out
is given by
Z
out
=
R
int
1
+
N
,
and the resistance R
int
is determined so that the output impedace Z
out
matches the line impedace R
L
seen by the amplifier
22
. Since the internal resistor
28
is provided within the two output stages
24
and
26
of the amplifier
22
, there is no matching resistor between the output node
25
of the amplifier
22
and the transformer. Therefore, the signal swing of the amplifier output (i.e., at the node
25
) is directly supplied to the transformer, and thus is reduced by half compared to the conventional structure (
FIG. 1
) as described above, thereby reducing the required power of the amplifier
22
.
A major drawback of the active termination structure shown in
FIG. 2
however is that the synthesized impedace has sensitivity to line impedance variations, because the second output transistor
26
is not inside the closed loop configuration, as shown in FIG.
2
. In the conventional active termination scheme
20
, the line impedance Z is assumed to be constant and thus the synthesized output impedance Z
out
has a fixed value so as to match the constant line impedance Z. However, the actual line impedance is not constant and varies with frequency, and the frequency dependency of a transmission line also varies with the type of the transmission line, resulting in a mismatch of the synthesized impedance. Such a mismatch between the synthesized impedance and the actual line impedance degrades the linearity of the amplifier.
Typical achieved linearity level using the traditional active termination structure is around 40 dB. This level of linearity may be sufficient for voice-band communications, however, it is not acceptable in broadband communication applications such as xDSL transceivers. There is no known approach to solve this problem employing full active termination. Accordingly, it would be desirable to provide means for compensate such line impedance variation so as to improve the linearity of an amplifier and a line driver used for broadband communications.
BRIEF DESCRIPTION OF INVENTION
A line driver for coupling a data Deceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit coupled with the input port, for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.
REFERENCES:
patent: 5121080 (1992-06-01), Scott, III et al.
patent: 5585763 (1996-12-01), Navabi et al.
patent: 5920468 (1999-07-01), Brisson et al.
patent: 6016084 (2000-01-01), Sugimoto
patent: 6163579 (2000-12-01), Harrington et al.
patent: 6211719 (2001-04-01), deBrigard
Mahadevan et al., “A Differential 160-MHz Self Terminating Adaptive CMOS Line Driver”, Dec. 2000, IEEE Journal of Solid-State Circuits, vol. 35, No. 12, pp. 1889-1894.
Bicakci Ara
Conroy Cormac S.
Kim Chun-Sup
Lee Sang-Soo
Tan Vibol
Thelen Reid & Priest L.L.P.
Tokar Michael
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