Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-04-28
2004-09-14
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06792563
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to failure analysis techniques for processors and, in particular, the present invention relates to bus activity tracking.
BACKGROUND
In the race to design higher performing and lower cost computers, processor designers have been making improvements in hardware components. As the number of transistors has increased from hundreds to millions, the speed and complexity of processors have increased, thereby increasing the probability of errors. Besides increasing integration, computer architecture has become more varied and creative over the years. In creating new architecture designs, sometimes the designer merges two separate electronic components together into one electronic component. When this happens, an interface between the two electronic components—once visible for test purposes—becomes hidden inside the single electronic component. When visibility is lost, errors in transactions over the interface become very difficult to debug.
For example, moving a cache onto the same die can decrease processor cache access time and is thus a desirable new design. In the old design, the bus between the cache and processor was debugged using a logic analyzer. In the new design with the cache inside the processor component, a logic analyzer can no longer reach the bus because the bus is inside a single component. Consequently, any error that occurs while using the cache is hidden and invisible, forcing the user (also referred to herein as a “debugger”) to rely on scant evidence from outside the component to make indirect inferences about the possible sources of the error. Furthermore, in the case of marginal failures, the failure must be reproduced for each test, but replicating the specific conditions leading to a marginal failure is difficult at best, especially when those conditions are invisible. Therefore, the user (debugger) has no hard data and only hunches and hypotheses about where an error may be occurring and what is literally occurring on the bus. Yet, hunches and hypotheses often waste valuable time and eventually lead to dead ends without a way to directly observe the function of the bus. In short, the user (debugger) needs a precise tool to observe bus traffic in order to diagnose and debug errors in bus activity efficiently. Quick failure analysis turnaround is necessary to support high-volume semiconductor manufacturing, where annual processor production volume is in the range of tens of millions of units.
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DesRosier Peter J.
Gupta Vikram
Patterson Dan W.
Beausoliel Robert
Bonzo Bryce P.
Schwegman Lundberg Woessner & Kluth P.A.
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