Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-03-24

2004-09-07

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S187000

Reexamination Certificate

active

06788565

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having DRAM cells using MIS transistors as means for accumulating charges and capable of high-speed data transfer.
As a large-capacity semiconductor memory device capable of holding a large amount of data, there has conventionally been used a semiconductor memory device having DRAM cells composed of capacitors for accumulating charges and switch transistors for transferring the charges to the capacitors. However, the structures of DRAM cells such as stacked DRAM cells have been increasingly complicated as semiconductor memory devices have been scaled down and increased in performance. In particular, increased manufacturing cost presents a problem when the semiconductor memory devices are used in system LSIs.
For a cost reduction, a semiconductor memory device using MIS transistors as means for accumulating charges has been developed in recent years.
Referring to the drawings, a semiconductor memory device disclosed in U.S. Pat. No. 5,600,598 will be described as a conventional example. The semiconductor memory device uses DRAM cells which accumulate charges in MIS transistors.
FIG. 11
shows a circuit structure of each of the DRAM cells of the semiconductor memory device according to the conventional example. A DRAM cell
200
shown in
FIG. 11
has a structure such that a channel is formed by applying a bias voltage Vcp to the gate of a first transistor
201
as an n-channel MIS transistor and charges are accumulated in a capacitance produced in the channel. In such a structure, if a second transistor
202
is turned ON by inputting a signal indicative of data to a bit line BL and driving a word line WL, charges are transferred between the bit line BL and the channel of the first transistor
201
so that the writing of the data is performed. If the second transistor
202
is turned ON, after precharging the bit line BL to a specified voltage, by driving the word line WL, a potential in the bit line BL changes depending on the presence or absence of charges in the channel of the first transistor
201
. By sensing and amplifying the potential change, the data is outputted to the bit line BL.
Since the first and second transistors
201
and
202
of the semiconductor memory device according to the conventional example are implemented as a planar structure, intricate fabrication techniques are unnecessary so that a reduction in fabrication cost is achievable.
However, the conventional semiconductor memory devices requires a given period of time until the specified potential is reached by the precharging operation after the word line WL is activated, the potential change in the bit line is sensed and amplified, and the data is read onto the bit line BL. If the DRAM cell
200
is accessed immediately after the activation period for the word line WL is completed, the potential on the bit line BL may affect the charges in the channel of the first transistor
201
and destroy the data. Thus, the conventional semiconductor memory device has the problem that the DRAM
200
cannot be accessed for a given period of time after a preceding access to the DRAM cell
200
and therefore it is difficult to increase a data transfer speed in write/read operations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to solve the foregoing conventional problem and thereby increase a data transfer speed in a semiconductor memory device using a MIS transistor as charge accumulating means.
To attain the object, a first semiconductor memory device according to the present invention comprises: a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to a portion of a source or drain of the first transistor, and a third transistor having a source or drain connected to another portion of the source or drain of the first transistor, the first transistor accumulating, in a channel thereof, a charge transferred from the second and third transistors.
In the first semiconductor memory device, the transfer of the charge from the second and third transistors to the first transistor can be controlled independently by using the two transistors. Accordingly, the first transistor can be accessed, after data transfer performed by using one of the second and third transistors, by the other transistor so that a data transfer speed is increased.
In the first semiconductor memory device, the first, second, and third transistors are preferably of the same conductivity type.
The arrangement obviates the necessity to provide an isolation between the memory cells so that a semiconductor memory device with a high data transfer speed is implemented at low cost.
In the first semiconductor memory device, the first, second, and third transistors are preferably p-channel transistors.
The arrangement achieves a reduction in leakage current in each of the first, second, and third transistors so that a semiconductor memory device with low power consumption and a high data transfer speed is implemented at low cost.
In the first semiconductor memory device, the first, second, and third transistors are preferably n-channel transistors.
The arrangement improves the mobility of the carrier in the channel of each of the first, second, and third transistors so that a semiconductor memory device capable of high-speed operation is implemented.
In the first semiconductor memory device, a predetermined voltage is preferably applied to a gate of the first transistor such that the first transistor is in a conductive state when a power supply is ON.
In the first semiconductor memory device, the first transistor is preferably of depletion type.
The arrangement reduces power consumption during the accumulation of the charge in the capacitance between the gate and channel.
Preferably, the first semiconductor memory device further comprises: a plurality of first word lines connected to respective gates of the second transistors of the plurality of memory cells; and a plurality of second word lines connected to respective gates of the third transistors of the plurality of memory cells, wherein activation of one of the plurality of first word lines and activation of one of the plurality of second word lines are initiated alternately.
In the first semiconductor memory device, one of the plurality of first word lines and one of the plurality of second word lines which are connected to different memory cells preferably have respective activation periods in overlapping relation and one of the plurality of first word lines and one of the plurality of second word lines which are connected to a same memory cell preferably have respective activation periods in non-overlapping relation.
In the first semiconductor memory device, one of the first and second word lines connected to the same memory cell which is activated earlier than the other is preferably brought into an inactivated state such that the activation period thereof does not overlap the activation period of the other word line.
Preferably, the first semiconductor memory device further comprises: a plurality of first bit lines connected to the respective sources or drains, which are not connected to the first transistors, of the second transistors; and a plurality of second bit lines connected to the respective sources or drains, which are not connected to the first transistors, of the third transistors, wherein the memory cells are arranged with an isolation region interposed therebetween in a direction in which the first and second word lines extend and are arranged in an indiscrete active region with the second and third transistors alternately interposed therebetween in a direction in which the first and second bit lines extend, each of contacts providing connections between the second transistors and the first bit lines is used commonly by the respective second transistors of the adjacent memory cells which are opposed to each other, and each of contacts providing connections between the third transistors and the second bit lin

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