Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-06
2004-03-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S300000, C438S242000
Reexamination Certificate
active
06707095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods of manufacturing semiconductor memory cells and more particularly to providing isolation between back-to-back MOSFET DRAM cells.
2. Description of Related Art
Present trends in Dynamic Random Access Memory (DRAM) technology are constantly driven towards reduction in minimum feature size “F”, where the value “F” represents the minimum feature structural dimension of the memory cell. Also the trends for DRAM devices are towards more compact cell layouts, i.e., denser than 8 F
2
, where the layout is the area required for a feature on the surface of the silicon substrate. Because of the need for ever increasing array densities, the scalability of contemporary planar metal oxide semiconductor field effect transistor (MOSFET) cells for smaller and smaller dimensions is facing fundamental concerns. The main concern with the scalability of the MOSFET cell is the increased P-well doping concentration needed to meet off-current objectives. It is well known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problem of scalability related to the MOSFET cell, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
There is a need for DRAM cells containing vertical access transistors with dense layouts and trench storage capacitors which yield sufficient capacitance and reduced series resistance to avoid degraded signal development.
Although some existing DRAM cells employing vertical MOSFETs offer very significant scalability advantages over conventional planar designs practiced today, there is still a great deal of room for improvement. For example, for cells using vertical MOSFETs and trench storage capacitors, a single bitline contact is commonly used to access a pair of bits; the pair of bits share a common silicon Active Area (AA). In this type of cell, dynamic coupling between the two back-to-back vertical MOSFETs results in charge pumping effects and loss of signal. Modeling has shown that electrons pumped into the P-well from a collapsing channel inversion layer of one cell may be collected by the storage node of the adjacent cell sharing the same AA. These coupling effects are accentuated as dimensions are scaled down. Modeling projections indicate that scalability to smaller and smaller dimensions will be problematic because of dynamic charge loss due to coupling between adjacent cell.
In addition to charge pumping problems, very dense prior art designs suffer from threshold voltage variations in the size of the silicon AA which occurs with overlay (alignment) errors between various masking levels and with dimensional variations of features formed by these masking levels.
Another problem faced with aggressively scaled DRAM cells is the increased aspect ratio (height to width) of the isolation regions. This is especially a concern with vertical MOSFETs in the array because of the requirement that the isolation trench be deep enough to cut the outdiffusion strap so as to prevent cell-to-cell leakage between straps. Typically, it is required that the isolation trench be at least 500 nm in depth to isolate the outdiffusion straps of the vertical MOSFETs. If the thickness of the pad layer is included, an isolation trench aspect ratio of 7:1 is anticipated by the 100 nm generation.
In view of the drawbacks mentioned hereinabove with prior art DRAM cell designs, there is a continued need to develop new and improved DRAM cell designs that are denser than prior art designs and have a larger DT size. A larger DT size is advantageous in dense DRAM cells since it provides a large storage capacitance and reduced series resistance to the array cell.
As indicated above, scaling of vertical MOSFET DRAM cells is limited by loss of data caused by dynamic coupling between back-to-back cells. For the existing structure and process, this mechanism may prevent the successful scaling of the 8 F
2
vertical MOSFET DRAM to 90 nm ground rules, where the value “F” represents the minimum feature size of the device, i.e. the dimension “F” is the minimum structural dimension of the memory cell.
U.S. Pat. No. 6,018,174 of Schrems et al. for “Bottle-Shaped Trench Capacitor with Epi Buried Layer” describes a bottle-shaped trench capacitor with an expanded lower trench portion and an epitaxial layer that is the buried plate of the trench capacitor. The patent states that “A conventional technique for forming the buried plate includes outdiffusing dopants into the substrate region surrounding the lower portion of the trench. One type of capacitor that is commonly employed in DRAMs is the trench capacitor. A trench capacitor is a three-dimensional structure formed in the substrate. Typically, a trench capacitor comprises a deep trench etched into the substrate. The trench is filled, for example, with n-type doped poly. The doped poly serves as one electrode of the capacitor (referred to as the “storage node”). An n-type doped region surrounds the lower portion of the trench, serving as a second electrode. The doped region is referred to as a “buried plate.” A node dielectric separates the buried plate and the storage node.
U.S. Pat. No. 6,163,045 Mandelman et al. for “Reduced Parasitic Leakage in Semiconductor Devices” describes a trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET enabling the use of a thinner collar while still achieving an acceptable level of leakage. The patent states that “Trench capacitors are commonly employed in DRAMs. A trench capacitor is a three-dimensional structure formed into the silicon substrate. A conventional trench capacitor comprises a trench etched into the substrate. The trench is typically filled with n+ doped poly which serves as one plate of the capacitor (referred to as the storage node). The second plate of the capacitor, referred to as a ‘buried plate,’ is formed by, for example, outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided therein.” The patent states further that “p-type dopants, such as boron (B) are implanted into the well region. The dopants are implanted sufficiently deep to prevent punchthrough and to reduce sheet resistance. The dopant profile is tailored to achieve the desired electrical characteristics, e.g., gate threshold voltage (V
T
)”. The device includes an arrangement referred to here as Bilateral BSOD (BBSOD) configuration, i.e. there are buried strap outdiffusion regions on both sides of the deep trench of the device, but it should be noted that there is only one isolated deep trench device shown in the device, so there is no showing of BSOD regions in a confrontational configuration in a P-well.
Commonly assigned U.S. Pat. No. 6,281,539 of Mandelman et al. for “Structure and Process for 6 F
2
DT Cell Having Vertical MOSFET and Large Storage Capacitance” describes a 6 F
2
memory cell comprising a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate. Each of a plurality of transfer transistors has a vertical gate dielectric, a gate conductor, and a bitline diffusion, and each transistor is located above and electrically connected to a respective trench capacitor. About the transistors are dielectric-filled isolation trenches spaced apart by a substantially uniform spacing in a striped pattern. A respective wordline is electrically contacted to each respective gate conductor.
The above Mandelman et al. U.S. Pat. No. 6,281,539 states as follows “To prevent unwanted formation of strap diffusion on the side of the trench which is adjacent to the oxide fill, a thin Si
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N
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barr
Chidambarrao Dureseti
Mandelman Jack A.
Radens Carl J.
Jones Graham S.
Schnurmann H. Daniel
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