Static RAM architecture with bit line partitioning

Details Static RAM architecture with bit line partitioning Static RAM architecture with bit line partitioning

2002-09-05

2004-03-23

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000, C365S189020

Reexamination Certificate

active

06711051

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of static random access memory (SRAM) arrays, and to a SRAM memory architecture providing for bit line partitioning.
BACKGROUND OF THE INVENTION
FIG. 1
shows a SRAM memory array architecture of the prior art. This architecture utilizes a six transistor memory cell
200
as shown in FIG.
2
. The six transistor SRAM bit cell
200
shown in
FIG. 2
utilizes a first supply voltage, VDD
217
, and a ground connection
218
. The cell also includes a word line WLC. Bit lines BTC and BBC provide a connection to read and write data to the cell. The bit cell also includes a storage cell which includes four transistors,
206
,
208
,
210
,
212
, configured to store data. As is known in the art, transistors
206
and
208
act as load transistors and transistors
210
and
212
act as cross coupled storage transistors. As shown in the bit cell
200
, the load transistors
206
and
208
are PMOS transistors, and storage transistors
210
and
212
are NMOS transistors. NMOS Transistors
214
and
216
arc word line, or row select, pass transistors.
In a static mode, when the cells in the memory array are not in write or read mode, bit lines BTC and BBC, shown in
FIG. 2
, are precharged to a VDD level, and the word line shown in
FIG. 2
as WLC is at logic zero. In this static state, a programmed cell can maintain the information equivalent to logic 0 or logic 1, since n-channel devices
214
and
216
are off, which isolates the storage cell that includes devices
206
,
208
,
210
and
212
.
In a write mode, the WLC line (e.g. WL
0
, WL
1
. . . WLN) which is coupled to a row of cells (e.g. N
00
, N
01
. . . N
0
M), as shown in
FIG. 1
, which contains the cell being written to, is driven to logic 1 or VDD to turn on (open) the pass transistors, thereby providing access to the storage cell. To write to the cell to be programmed to store a binary
1
, the bit line BTC for the cell being written to is driven to logic 1, and the bit line BBC is driven to logic 0. This results in the cell being programmed to logic 1, where the voltage at node
202
will be set at logic 1 and the voltage at node
204
will be set at logic 0 as is known in the art. To program the cell to logic 0 the bit line BTC is driven to logic 0 and the bit line BBC is driven to logic 1, such that
202
will be set at logic 0 and
204
will be set at logic 1 as is known in the art.
In the static mode, in between read and write operations, the bit lines BTC and BBC are held at a precharge voltage VDD using the PMOS transistors
102
of the precharge circuit
106
shown in FIG.
1
. In the static mode the word line (WL
0
, WL
1
, . . . WLN) pass transistors
214
and
216
shown in
FIG. 2
are held closed as the WLC voltage is at logic zero.
To read the data from the cell the WLC voltage is changed to logic 1. The signal of voltage logic 1 on WLC is applied to the gates of the word line pass transistors
214
and
216
, which opens the word line pass transistors
214
and
216
, so that current can flow through the transistors. In addition to the WLC voltage being set to logic 1, the precharge circuit
106
is closed so that the bit lines BTC and BBC are allowed to float. With the word line pass gate transistors open, one of the bit lines BTC and BBC will discharge depending on which node
202
or
204
is at zero. For example, if the cell is programmed at logic 0 then the BTC bit line will discharge through the NMOS transistor
214
and the cross coupled storage transistor
210
, and BBC would remain floating at the VDD level. If the cell was programmed at logic 1 then BBC would discharge through
216
and
212
, and BTC would remain at VDD. The switch (SW
0
, SW
1
. . . SWM) connected to the cell which is being read will be closed (conductive) and the sense circuitry
104
will read the difference in voltage in the bit lines BTC and BBC to determine whether the data is
1
(one) or
0
(zero).
In the prior art Static Random Access (SRAM) memory architecture
100
as shown in
FIG. 1
, there are three stages of operation. At stage
1
memory read/write operations require that all bit lines (BT
0
, BB
0
, BT
1
, BB
1
, . . . BTM, BBM) be precharged to logic 1 by the precharge circuitry
106
, the precharge circuitry provides PMOS transistors
102
, which in the static mode are opened by a PRCHG voltage signal
108
being at logic 0, which is applied to the gates of the PMOS transistors
102
. Also all word lines (WL
0
, WL
1
. . . WLN) are set to logic 0 before read read/write operation for any cell occurs.
At stage
2
of the memory read/write mode all are of the PMOS transistors
102
are closed (PRCHG voltage
108
is set to logic 1), so that the voltage on the bit lines is allowed to float, instead of being held at VDD. One of the word lines (e.g. WL
0
) is driven to logic 1 All the 6T (6-transistor)core memory cells (e.g. bit cells N
00
, N
01
. . . N
0
M) coupled to this word line begin to discharge the bit lines (e.g. BT
0
, BB, BT
1
, BB
1
. . . BTM, BBM). The discharge of the bit lines at this stage causes a large active AC power dissipation.
Stage
3
of the memory bit cell read/write operation is selecting one of the switches (SW
0
, SW
1
. . . SWM) in the MUX block
103
by setting Y
0
, Y
1
. . . or YM to logic 1. As shown in
FIG. 1
, Y
0
is selecting column
1
. To write data to a bit cell at this stage requires using a write circuit
104
to program the selected individual bit cell, by applying a voltage differential to bit lines BT
0
and BB
0
. (The write circuitry and sense circuitry is known to one of skill in the art, and shown as block
104
in
FIG. 1.
) To read data from the bit cell requires amplifying the differential signal between the bit lines BTC and BBC using a sense amplifier and then routing this to an output circuit.
Regardless of which mode is used, whether read or write, a bit line for each column of SRAM memory bit cells of the complete array will be discharged during every read/write operation, and before a new read/write cycle can begin, and the array has to precharged again. This is because the same PRCHG signal is applied to the gates of all of the PMOS transistors
102
of the precharge circuit
106
, and all of the bit cells coupled to word line with logic 1 have word line pass transistors (e.g.,
214
and
216
) which are opened as a result of the word line generating a logic 1 signal. Stated another way, all the bit lines have to precharged again because all have been discharged during the read/write operation.
One problem with this prior approach is that, for each read/write cycle, enough power to precharge and discharge all of the bit line pairs in the array is consumed, while all that is really needed is to program or read information for one bit line pair (e.g. BTC and BBC) during each read or write cycle.
As disclosed in the patent application filed on Apr. 9, 2002, entitled LOW POWER STATIC RAM ARCHITECTURE (U.S. application Ser. No. 10/119,191) which has common inventors to the present application, and is assigned to the National Semiconductor Corporation, the assignee of the present application, one approach to reduce the power consumed during each read write cycle is to implement an 8 bit memory cell where a column select signal can be used in conjunction with the a word select signal to limit the power discharge during each cycle to a particular column. The U.S. application Ser. No. 10/119,191 referred to above is hereby incorporated by reference in its entirety. As further discussed in the pending patent application Ser. No. 10/215,678 filed on Aug. 10, 2002, entitled LOW AC POWER STATIC RAM ARCHITECTURE, and in the pending patent application Ser. No. 10/215,676 filed on Aug. 10, 2002, entitled BIT LINE SHARING AND WORLD LINE LOAD REDUCTION FOR LOW AC POWER SRAM ARCHITECTURE the SRAM architecture can be further modified to decrease power consumption by providing for word line and bit line sharing and by providing for sector selection where sections of the columns of memory cells can be selected

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