Synchronous semiconductor device with memory chips in a module f

Details Synchronous semiconductor device with memory chips in a module f Synchronous semiconductor device with memory chips in a module f

1997-08-25

1999-08-17

Nelms, David

Static information storage and retrieval

Read/write circuit

36518904, 365195, 365191, G11C 1604

Patent

active

059403284

ABSTRACT:
One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.

REFERENCES:
patent: 5513135 (1996-04-01), Dell et al.
patent: 5696732 (1997-12-01), Zagar et al.

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