Ferroelectric memory device and method of forming the same

Details Ferroelectric memory device and method of forming the same Ferroelectric memory device and method of forming the same

2002-01-30

2004-05-18

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S298000, C257S310000, C257S532000, C438S239000, C438S396000

Reexamination Certificate

active

06737694

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-6813, filed on Feb. 12, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a ferroelectric memory device and a method of forming ferroelectric memory devices. More specifically, the present invention is directed to a ferroelectric memory device having a ferroelectric capacitor connected to a buried contact structure, as wells as a method of forming that device.
2. Description of Related Art
In current data processing systems, a Random Access Memory (RAM) is used to provide high-speed access to data, which is stored in the memory. Because the semiconductor industry is in continuous need of memory devices having even higher operation speeds, studies have been conducted on the use of a Ferroelectric Random Access Memory (hereinafter referred to as “FRAM”). A ferroelectric layer formed between capacitor electrodes provides a FRAM with non-volatile characteristics. In other words, the FRAM has two stable polarization states, represented by a hysterisis loop.
The FRAM has several advantages over other RAM devices. It has non-volatile characteristics as a flash memory. It also uses a relatively low operation voltage (approximately 5V), and has excellent operation speed (dozens of nanoseconds). In order to be usable in modern semiconductor products, however, FRAM devices must be highly integrated.
Like a dynamic random access memory (DRAM), the FRAM includes a transistor and a capacitor. The capacitor is a ferroelectric capacitor having a ferroelectric layer. The ferroelectric capacitor must be electrically connected to the transistor. Several approaches have been used to provide the electric connection between the capacitor and the transistor. One approach, disclosed in U.S. Pat. No. 5,119,154, uses a metal to provide a local interconnection. Unfortunately, this local interconnection approach is not suitable for high-density FRAMs because the local interconnection is fairly large and the size of the unit memory cells in high-density devices must be minimized.
Another approach uses a contact plug made of a conductive material to connect a source region of the transistor to the ferroelectric capacitor. The contact plug connection approach, disclosed in U.S. Pat. Nos. 5,854,104 and 5,591,663, has been widely used in the production of high-density FRAMs.
FIG. 1
is a schematic cross-sectional view of a conventional ferroelectric memory device constructed using the conventional contact plug connection approach.
Referring to
FIG. 1
, a memory cell of a conventional FRAM includes a transistor
104
located on a semiconductor substrate
10
. The transistor
104
has a drain region
106
a
, a source region
106
b
, and a gate electrode (not shown). A first interlayer insulating layer
108
is formed and planarized on the transistor
104
and the substrate
100
. A bit line
112
is then formed on the first interlayer insulating layer
108
. The bit line
112
is electrically connected to the drain region
106
a
through a predetermined part of the first interlayer insulating layer
108
.
A second interlayer insulating layer
114
is formed on the first interlayer insulating layer
108
and the bit line
112
. A contact hole
118
is formed through a predetermined region of the second and first interlayer insulating layers
114
,
108
. A contact plug
119
is formed in the contact hole
118
. A ferroelectric capacitor
126
is formed on the second interlayer insulating layer
114
in electrical contact with the contact plug
119
. A third interlayer insulating layer
128
is then formed on the second interlayer insulating layer
114
and the ferroelectric capacitor
126
. The ferroelectric capacitor
126
is electrically connected to the source region
106
b
via the contact plug
119
formed through the second and first interlayer insulating layers
114
,
108
.
To form the contact plug
119
, the first and second interlayer insulating layers
108
,
114
must be etched to form the contact hole
118
. Unfortunately, however, the first and second interlayer insulating layers
108
,
114
are fairly thick, having thicknesses of about 4000 Å-6000 Å and 3000 Å-5000 Å, respectively. Furthermore, as the integration level of the semiconductor devices increases, the diameter of the contact holes decreases while an aspect ratio thereof increases. As a result, the contact hole
118
must be narrow and deep.
It is difficult to etch the narrow and deep contact hole
118
. Problems such as a closed contact hole or an over-etched source region can occur. It is also difficult to fill the narrow and deep contact hole
118
with a conductive material, such as tungsten (W), having improved electric conductivity. Materials with better deposition characteristics, such as polysilicon, are therefore used to fill the contact hole
118
. Polysilicon, however, is more resistive than tungsten (W) and therefore provides an inferior contact plug.
Still referring to
FIG. 1
, after the contact hole
118
is filled with polysilicon, it is then planarized down to a top surface of the interlayer insulating layer
114
to form a contact plug. Thereafter, a lower electrode
120
, a ferroelectric layer
122
, and an upper electrode
124
are formed and patterned over the contact plug
119
to form a ferroelectric capacitor
126
that is electrically connected to the contact plug
119
.
A contact area between a polysilicon contact plug
119
and a lower electrode
120
is determined based upon a diameter of the contact hole
118
. Since the diameter of a contact hole decreases as the integration of semiconductor device increases, however, it is difficult to secure a stable electrical contact between a lower electrode and a contact plug in high-density devices. Securing a stable contact in highly-integrated devices is a significant task.
In a conventional process of forming a ferroelectric layer
122
of the capacitor
126
, a ferroelectric material is deposited and annealed in a high-temperature oxygen ambient. Through this process, the crystalline state of the ferroelectric material is thereby changed to a perovskite ferroelectric crystalline state. The high temperature used for this process is around 550° C. or higher. Annealing in an oxygen ambient is important in many steps of the semiconductor integration process. Unfortunately, this annealing process also causes the formation of a thin insulating layer (e.g., a silicon dioxide (SiO
2
) layer) at an interface between the polysilicon contact plug and the lower electrode. This undesired byproduct can make it difficult to secure good contact between the contact plug and the lower electrode and result in a contact failure.
The conventional polysilicon contact plug approach for providing the connection between the ferroelectric capacitor and the transistor in the FRAM memory device is unable to provide the contact stability necessary to enable the high integration levels desired by the industry. The industry would be benefited by a ferroelectric memory device that improves the stability of the contact and therefore the integration level of the FRAM. A corresponding method is also desirable.
SUMMARY OF THE INVENTION
According to preferred aspects of the present invention, a lower electrode of a ferroelectric capacitor is electrically connected to a source region of a transistor through a buried contact structure that can be formed concurrently with a bit line. The buried contact structure therefore makes it possible to simplify the process steps.
In addition, an oxidation barrier layer is formed on the buried contact structure to prevent oxygen from contacting the buried contact structure during subsequent annealing in a high-temperature oxygen ambient. Also, where the buried contact structure is made of tungsten (W), for example, the formation of silicon dioxide (SiO
2
) thereon is prevented.
Also, since the diameter of a top of the contact struct

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