Memory integrated circuit

Details Memory integrated circuit Memory integrated circuit

2002-06-20

2004-09-21

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06795329

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits (ICs). More particularly, the invention relates to memory ICs, for example, ferroelectric memory ICs, with series architecture.
BACKGROUND OF THE INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalate (SBT) can also be used.
FIG. 1
shows a conventional ferroelectric memory cell
105
having a transistor
130
and a ferroelectric capacitor
140
. A capacitor electrode
142
is coupled to a plateline
170
and another capacitor electrode
141
is coupled to the transistor
130
which selectively couples or decouples the capacitor from a bitline
160
, depending on the state (active or inactive) of a wordline
150
coupled to the transistor gate.
The ferroelectric memory stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 2
shows a plurality of ferroelectric memory cells configured in a chain
202
. Such a memory architecture is described in, for example, Takashima et al., Symposium on VLSI Circuits (1997), which is herein incorporated by reference for all purposes. The memory cells
205
of the chain, each comprises a transistor
230
coupled to a capacitor
240
in parallel, are coupled in series. Gates
233
of the cell transistors, for example, are gate conductors which serve as or are coupled to wordlines. One end
208
of the chain is coupled to a bitline while the other end
209
is coupled to a plateline. A plurality of chains are interconnected by wordlines to form a memory block or array.
FIG. 3
shows a conventional cross-section of a memory chain
302
. As shown, the transistors
330
of the memory cells
305
are formed on a substrate
310
. Adjacent cell transistors shared a common diffusion region. The capacitors
340
of the memory chain are grouped in pairs. The bottom electrode
341
serves as a common electrode for adjacent capacitors. The top electrode
342
of a capacitor from a capacitor pair is coupled to the upper electrode of a capacitor of an adjacent pair, thus forming a daisy chain. The top capacitor electrodes are coupled to the cell transistors via active area top electrode plugs
386
.
During standby or when the memory chain is not selected for a memory access, the wordlines of the chain are active to render the cell transistors of the chain conductive. The capacitors of the chain are shorted when transistors are conductive. To retrieve or read information from one memory cell of the chain, a pulse (e.g., 2.5V) is provided at the plateline. The wordline corresponding to the row address of the memory access is deactivated, causing the transistor of the selected cell to be non-conductive. As a result, the pulse produces an electric field across the capacitor of the selected cell.
Due to the sharing of diffusion regions between adjacent cell transistors and sharing of top and bottom electrodes of adjacent cell capacitors, the electric field will be in different directions for adjacent cells. As indicated, even addressed memory cells will have an electric field applied in a first direction while odd addressed memory cells have an electric field in a second or opposite direction. Alternating external electric field directions across capacitors for odd and even addresses results in an asymmetrically shaped hysteresis curves for odd and even addresses. As a result, the read signal for odd and even address locations will be different. This leads to a broadening of read signal distributions, as shown in
FIG. 4
, undesirably reducing sensing window.
From the foregoing discussion, it is desirable to provide an improved chained architecture which avoids asymmetrical hysteresis curves for odd and even address locations.
SUMMARY OF THE INVENTION
The invention relates to memory ICs. The memory cells are arranged in a chain memory having x memory cells. A memory comprises a transistor having first and second diffusion regions and a capacitor having dielectric layer between first and second electrodes. One of the electrodes is a bottom electrode and the other one is a top electrode. The first electrode is coupled to the first diffusion region and the second electrode is coupled to the second diffusion region.
In one embodiment, the memory cells are ferroelectric memory cells in which the ferroelectric capacitors each comprises a ferroelectric layer between the first and second electrodes. The cell transistors, for example, are n-FETs.
In one embodiment, the memory cells are interconnected by having the second electrode of the k
th
memory cell of the chain coupled to the first electrode of the k
th
+1 memory cell of the chain. By interconnecting the memory cells of the chain in such a manner, the electric fields applied across any of the capacitors of the chain by a plateline pulse are in the same direction. As a result, the memory cells of the chain produce more symmetrical hysteresis curves, thereby improving the sensing window.


REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 2003/0142534 (2003-07-01), Takashima

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