Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-12-12
2004-04-06
Deppe, Betsy L. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C332S127000, C332S128000, C331S025000
Reexamination Certificate
active
06717998
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency synthesizer apparatus equipped with a fraction part control circuit, a communication apparatus, a frequency modulator apparatus, and a frequency modulating method each utilizing the frequency synthesizer apparatus. In particular, the present invention relates to a frequency synthesizer apparatus comprising a phase-locked loop circuit (hereinafter referred to as a PLL circuit) and a fraction part control circuit, which utilizes the PLL circuit to control a fraction part of a number of frequency division inputted to a variable frequency divider provided in the PLL circuit, a communication apparatus, a frequency modulator apparatus, and a frequency modulating method each utilizing the frequency synthesizer apparatus.
2. Description of the Related Art
Generally speaking, an output frequency of a frequency synthesizer apparatus using a PLL circuit is expressed by a quotient that is calculated by dividing a reference signal frequency by a number of frequency division set in a variable frequency divider. Since a general variable frequency divider can set only the number of frequency division as integer data, the output frequency is equal to an integral multiple of the frequency of the reference signal, and thus, the output frequency cannot be set to a unit that is smaller than the frequency of the reference signal. Therefore, the frequency of the reference signal must be lowered when it is necessary to set the output frequency at shorter frequency intervals. However, the lower reference signal frequency causes a larger number of frequency division of the variable frequency divider, and noise occurring in an output signal also increases as the number of frequency division increases. Since a response bandwidth of the PLL circuit cannot be wider than that of the frequency of the reference signal, a response speed of a loop of the PLL circuit decreases, and this leads to the period of switching over between frequencies to increase.
A method for obtaining a number of frequency division having decimal precision by using a general variable frequency divider has been known as a method for solving the above-mentioned problems. This method is provided for realizing a number of frequency division having a decimal precision as average data by periodically changing the number of frequency division. This method utilizes a delta-sigma modulator circuit (or a &Dgr;-&Sgr; modulator circuit: sometimes called a sigma-delta modulator circuit (or a &Dgr;-&Sgr; modulator circuit)).
FIG. 19
is a block diagram showing a circuit configuration of a frequency synthesizer apparatus of the prior art. The frequency synthesizer apparatus is provided for realizing a number of frequency division having decimal precision.
Referring to
FIG. 19
, the frequency synthesizer apparatus comprises a voltage control oscillator
1
(hereinafter referred to as a VCO), a variable frequency divider
2
(or frequency demultiplier), a phase comparator
3
, and a low-pass filter
4
including a loop filter, which are connected in a loop configuration. The frequency synthesizer apparatus further comprises a fraction part control circuit
80
and an adder
6
. The variable frequency divider
2
divides the frequency of an output signal from the VCO
1
in accordance with input data of a number of frequency division, and then outputs the frequency-divided signal to the phase comparator
3
. The phase comparator
3
performs a phase comparison between an input reference signal and the output signal from the variable frequency divider
2
, and then outputs a signal indicating the result of phase comparison to the VCO
1
through the low-pass filter
4
. Thus, a PLL circuit is feedback-controlled so as to stabilize the output frequency of the VCO
1
.
Referring to
FIG. 19
again, the fraction part control circuit
80
comprises an adder
81
and a delay circuit
82
. The adder
81
adds data of a fraction part F inputted from an external apparatus to output data from the delay circuit
82
, and then outputs the resultant addition data to the delay circuit
82
. The delay circuit
82
is a latch circuit which operates by using the output signal from the variable frequency divider
2
as a clock. The adder
6
adds an output signal indicating an overflow of the adder
81
, i.e., a carry signal (indicating data of the controlled fraction part F), to data of an integral part M inputted from the external apparatus, and then inputs and sets resultant addition data as data of a number of frequency division in the variable frequency divider
2
.
In the frequency synthesizer apparatus of
FIG. 19
configured as described above, when a fraction part is equal to F, data of the output signal from the adder
81
increases by the fraction part F every clock period. When the adder
81
overflows as a result of a data L, the adder
81
overflows F times for a period of L clocks, and generates the carry signal.
FIG. 20
is a block diagram of a detailed configuration of the fraction part control circuit
80
shown in
FIG. 19
, showing the configuration using a z-transformation. In
FIG. 20
, z
−1
represents the delay of one clock. Output data Y from the fraction part control circuit
80
is expressed by the following Equation (1).
Y=F/L
+(1
−z
−1
)
Q
(1)
An operation of the fraction part control circuit
80
is equivalent to that of a first-order delta-sigma modulator circuit. Generation of the carry signal is equivalent to quantization using a quantization step L.
Referring to
FIG. 20
, the fraction part control circuit
80
comprises an adder
91
, a delay circuit
92
, a quantizer
93
, a multiplier
94
and a subtracter
95
. The adder
91
corresponds to the adder
81
shown in FIG.
19
. The delay circuit
92
corresponds to the delay circuit
82
shown in FIG.
19
. The subtracter
95
subtracts output data from the multiplier
94
from data of the fraction part F inputted from the external apparatus, and then outputs resultant subtraction data to the adder
91
. The adder
91
adds an output signal from the delay circuit
92
to an output signal from the subtracter
95
, and then outputs the result of addition to the delay circuit
92
and the quantizer
93
. The quantizer
93
quantizes an output signal from the adder
91
using the quantization step L, and then outputs the quantized signal. The multiplier
94
multiplies the output signal from the quantizer
93
,by the quantization step L, and then outputs a resultant multiplication signal to the subtracter
95
.
FIG. 21
shows timing charts of an operation of the frequency synthesizer apparatus shown in
FIG. 19
, where FIG.
21
(
a
) is a timing chart showing a change over time in a number of frequency division inputted to the variable frequency divider
2
, and FIG.
21
(
b
) is a timing chart showing a change over time in a control voltage to the VCO
1
.
As is apparent from FIG.
21
(
a
), the data corresponding to a number of frequency division is equal to M when no carry signal is generated, and the data of a number of frequency division is equal to M+1 when a carry signal is generated. Accordingly, average data is equal to (M+F/L) during L clock periods. Therefore, an output frequency of the VCO
1
is equal to an (M+F/L) multiple ((M+F/L)-fold or (M+F/L) times) of a frequency of a reference signal. Thus, the data of the fraction part F is changed, and this leads to the output frequency of the VCO
1
being set to an output frequency at an interval of 1/L of the frequency of the reference signal.
In the frequency synthesizer apparatus which utilizes the delta-sigma modulator circuit of the prior art to realize an output frequency equaling a non-integral multiple of a reference signal frequency with decimal precision, the data of a number of frequency division periodically changes at an interval of a basic period of L clocks (a changing period &Dgr;P) as shown in FIG.
21
(
a
). As shown in FIG.
21
(
b
), an output si
Adachi Hisashi
Hirano Shunsuke
Kosugi Hiroaki
Maeda Masakatsu
Nakatani Toshifumi
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