Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-27
2004-05-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06740926
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a planar transistor structure that minimizes resistance in the source region and simplifies fabrication of the semiconductor device.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) technology uses shallow, refilled trenches for isolating devices of the same type as replacements for LOCOS isolation. The process begins by defining columns of active areas for the transistors and isolation areas separating the active areas on the silicon substrate. Recesses are then etched into the isolation areas to form shallow trenches in-between the active areas. An isolation core Vt implant is performed to complete the isolation. After the implant, tunnel oxide is deposited over the silicon substrate and planarized such that it remains only in the trenches. After the tunnel oxide is etched, a layer of type-1 polysilicon (Poly1) is patterned over the source/drain regions to form columns of Poly1. A layer of oxide nitride (ONO) is then deposited over the substrate, followed by a layer of type-2 polysilicon (Poly2). A stack gate mask and etch is then performed to form stacked gate structures for the transistors using the Poly1 and Poly2, and to form word lines interconnecting transistors in each row using the Poly2.
FIG. 1A
is a top view of a conventional semiconductor device having a Poly2 stack gate structure. The semiconductor device
10
comprises an array of transistors
12
, which are located in active areas
14
of a silicon substrate. The active areas
14
are separated from one another by isolation regions
16
. As stated above, shallow trench isolation (STI) is used to isolate the columns of transistors
12
by etching trenches
16
into the substrate
18
. Each transistor
12
includes a drain
20
and a base layer of Poly1
22
. Each row of transistors
12
is interconnected by a layer of Poly2
24
, which also forms the top layer of the stack gate for each transistor
12
. Each transistor
12
and its drain
20
are located in the core region
26
of the substrate. A source region
28
lies adjacent to the layer of Poly2
24
that interconnects a particular row of transistors
20
. The source region
28
is also referred to as a voltage source-side region (Vss). The drains
20
of the transistors
12
are connected to a Vss contact
30
in the source region
28
.
FIG. 1B
is a cross-sectional view of the source region
28
of the semiconductor. In the source region
28
, the Poly1
22
and Poly1
24
have been removed, leaving only the trenches
16
filled with oxide (not shown) in the isolation region
16
. To make an electrical path so that current can flow from the drain
20
to the Vss contact
30
, a process called a self aligned source (SAS) etch is performed in the source region
28
. During the SAS etch, a Vss etch mask is patterned over the substrate, followed by an oxide etch that removes the oxide from the trenches
16
. An implant Vss mask is then patterned over the substrate, followed by a N+ implant, which forms a N+ junction in the source region
28
.
Although this process effectively forms an electrical path in the source region
28
, the process results in the source region
28
having high resistance for the connection between the drains
20
and the Vss contact
30
. In order to adequately isolate the transistors
12
, the trenches
16
have to be a certain depth (FIG.
1
B). This depth adds a linear length to the electrical path in the N+ junction. In some implementations, as much as 5× is added to the linear dimension. This added linear dimension increases resistance and reduces performance of the transistors
12
. In addition, fabrication of the semiconductor device
10
requires two Vss masks; one for the oxide etch and another for the N+ implant, which adds to the number of processing steps and time required to produce the device
10
.
An alternative to shallow trench isolation is LOCOS (LOCal Oxidation of Silicon) isolation in which field oxide (FOX) regions are grown in the substrate between the active areas to isolate the transistors. However, the FOX regions are vertically taller than the surrounding substrate, which also would increase the linear length of the electrical path in the source region
28
.
Accordingly what is needed is a transistor structure that minimizes the resistance of the source region and simplifies fabrication. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a planar transistor structure that minimizes resistance in the source region and simplifies fabrication of the semiconductor device. The device includes a row of transistors where each transistor includes a stack gate structure and a drain, and a layer of type-2 polysilicon is used to interconnect the transistors in each row. A source region is provided adjacent to the layer of type2 polysilicon that includes a contact and a N-type junction extending across the source region that provides a planar electrical path between the drains of the transistors and the contact.
According to the system and method disclosed herein, the planar source region improves resistance of the source region, and thereby increases overall performance of the semiconductor device.
REFERENCES:
patent: 5235200 (1993-08-01), Komori et al.
Advanced Micro Devices , Inc.
Loke Steven
Winstead Sechrest & Minick P.C.
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