Semiconductor storage element

Details Semiconductor storage element Semiconductor storage element

2002-03-28

2004-01-20

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S321000, C257S325000

Reexamination Certificate

active

06680505

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2001-093833 and No. P2001-093834, filed on Mar. 28, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage element.
2. Discussion of the Background
In recent years, an electrically erasable and programmable memory (hereinbelow, expressed as “nonvolatile memory”) has been developed as the storage media of portable information equipment etc. so as to become lower in its drive voltage and larger in its storage capacity, owing to the features that it can store information even after the cutoff of a supply voltage by storing charges, and that it is small in size and light in weight without requiring a driving component as in a magnetic disk.
FIG. 1
shows a sectional view of such a nonvolatile memory cell in the related art.
The nonvolatile memory cell includes a p-type silicon substrate
1
, a first tunnel insulator layer (tunneling film)
2
(2 nm thick) made of a silicon oxide film and formed on the silicon substrate
1
, an intrinsic polycrystal silicon layer
3
(5 nm thick) formed on the first tunnel insulator layer
2
, a second tunnel insulator layer (tunneling film)
4
(2 nm thick) made of a silicon oxide film and formed on the polycrystal silicon layer
3
, a floating electrode (floating gate)
5
(100 nm thick) made of n
+
-type polycrystal silicon and formed on the second tunnel insulator layer
4
, a control insulator layer
6
(10 nm thick) made of silicon oxide and formed on the floating electrode
5
, a control electrode (control gate)
7
(500 nm thick) made of n
+
-type polycrystal silicon and formed on the control insulator layer
6
, a channel region
10
which is located directly under the first tunnel insulator layer
2
within the silicon substrate
1
, and a source region
8
and a drain region
9
which are made of n
+
-type silicon and which are arranged in opposition within the silicon substrate
1
so as to hold the channel region
10
therebetween.
In the structure, the source region
8
, the drain region
9
, and the channel region
10
held between them as are located on the side of the silicon substrate
1
function as an n-channel field effect transistor.
Besides, the polycrystal silicon layer
3
which is sandwiched in between the first tunnel insulator layer
2
and the second tunnel insulator layer
4
is formed of microcrystals satisfying a Coulomb blockade condition, and charges such as electrons or holes can be transferred between the front surface of the silicon substrate
1
and the floating electrode
5
by tunneling. The “Coulomb blockade condition” signifies that the charge energy of one electron or hole is greater than a thermal fluctuation.
The floating electrode
5
is an electrical floating region which is electrically insulated by the second tunnel insulator layer
4
and the control insulator layer
6
, and which can store charges.
The writing method of the nonvolatile memory is so implemented that, when a voltage of about 10V is applied across the silicon substrate
1
and the control electrode
7
, electrons (carrier electrons in an inversion layer), for example, are drawn as the charges from the channel region
10
into the floating electrode
5
through a stacked structure comprising the first tunnel insulator layer
2
, polycrystal silicon layer
3
and second tunnel insulator layer
4
, by a quantum-mechanical tunneling phenomenon.
Besides, the reading method decides “1” or “0” by detecting a current which flows from the source region
8
into the drain region
9
when voltages are applied across the source region
8
and the drain region
9
and across the source region
8
and the control electrode
7
, and the value of which differs between in a state where the electrons have been injected into the floating electrode
5
to negatively charge this electrode and in a state where the electrons have not been injected.
Further, the erasing method is so implemented that the electrons in the floating electrode
5
are drawn out therefrom into the channel region
10
in accordance with the quantum-mechanical tunneling phenomenon by applying a voltage of about 10V across the silicon substrate
1
and the floating electrode
5
.
In such a nonvolatile memory, it is important that the charges stored in the floating electrode
5
are prevented from tunneling out even after the supply voltage has been cut off.
Meanwhile, semiconductor integrated circuits have hitherto been highly packaged owing to the progress of semiconductor microfabrication technology, and the nonvolatile memory as stated above is not exceptional. Also in the field effect transistor portion, the length of the channel region
10
, the thickness of the first tunnel insulator layer
2
, and the junction depth of the source region
8
as well as the drain region
9
have been reduced owing to the microfabrication of semiconductor elements.
According to the nonvolatile memory shown in
FIG. 1
, even when the tunnel insulator layers
2
and
4
are thinned to the extent of several nm, the electrons can be somewhat prevented from tunneling out after the cutoff of the supply voltage owing to utilizing a Coulomb blockade effect in silicon particle in layer
3
, and the microfabrication of the element can be incarnated.
Even with such a nonvolatile memory, however, the charges tunnel out when the memory is let stand for a long time, and a long storage time sufficient for practical use has not been realized yet.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem, and has for its object to provide a semiconductor storage element which realizes a sufficiently long storage time fit for practical use.
In the first aspect of performance of the present invention, there is provided a semiconductor storage element comprising:
a semiconductor layer;
a source region and a drain region formed in said semiconductor layer;
a channel region formed between said source region and said drain region;
a control electrode formed over said channel region; and
a stacked structure disposed between said channel region and said control electrode, the stacked structure including a conductive particle layer containing conductive particles, and a layer having an energy level allowing a charge to stay thereat;
wherein, when the charge is an electron, an energy level at which the electron is injected into the conductive particle or the layer having the energy level allowing the charge to stay thereat, as a charge stored layer, is lower than an energy level of a conduction band edge of said channel region or a Fermi level of said control electrode; and
when the charge is a hole, an energy level at which the hole is injected into the conductive particle or the layer having the energy level allowing the charge to stay thereat, as a charge stored layer, is higher than an energy level of a valence band edge of said channel region or the Fermi level of said control electrode.
Besides, in the second aspect of performance, there is provided a semiconductor storage element:
a semiconductor layer;
a source region and a drain region formed in said semiconductor layer;
a channel region formed between said source region and said drain region;
a first tunnel insulator layer formed on said channel region;
a conductive particle layer formed on said first tunnel insulator layer, the conductive particle layer containing conductive particles satisfying a condition that electrostatic energy in the case of charging one elementary charge is greater than a thermal fluctuation;
a second tunnel insulator layer formed on said conductive particle layer;
a charge stored layer formed on said second tunnel insulator layer; and
a control electrode formed on said charge stored layer;
wherein, when the charge is an electron, an energy level at which the electron is injected into said charge stored lay

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