FIFO memory device suitable for data transfer apparatuses...

Details FIFO memory device suitable for data transfer apparatuses... FIFO memory device suitable for data transfer apparatuses...

1999-09-01

2004-01-20

Bataille, P. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Varying address bit-length or size

C365S219000, C365S189050, C710S307000

Reexamination Certificate

active

06681314

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a FIFO memory device and a method for controlling such a FIFO memory device, and more particularly it relates to a FIFO that is suitable for data transfer between data processing apparatuses that have different data bus widths, and a method for controlling such a FIFO.
2. Description of the Related Art
One known FIFO and FIFO control method used for data transfer between data processes apparatuses having different data bus widths are, for example, the ones disclosed in Japanese Unexamined Patent Publication (KOKAI) No.4-64988.
FIG. 17
is a block diagram of the above-noted prior art, this drawing showing a device that enables (N×k) bit writing and k-bit reading.
In the above-noted prior art, however, there is an arbitration function that prevents simultaneous access of the memory from the input port and the output port. For this reason, the device is not suitable for high-speed data processing.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to improve on the above-noted drawback of the prior art, by providing a FIFO memory device that not only enables simultaneous reading and writing without having to perform bus arbitration, but also prevents skipped writing and double reading of data. It is a further object of the present invention to provide a method for controlling the above-noted FIFO memory device.
To achieve the above-noted object, the present invention has the following basic technical constitution.
Specifically, the first aspect of a FIFO memory device according to the present invention is used in data transfer between data processing apparatuses having different data bus widths from each other, comprising: an input circuit of said device with a data bus width of M×k bits (where M and k are integers greater than 1); an output circuit of said device with a data bus width of N×k bits (where N is an integer greater than 1, but being different from said M) that outputs read-out data from a memory provided within said FIFO memory device; a writing pointer that points to a data writing address of said FIFO memory device; a reading pointer that points to a data reading address of said FIFO memory device; and a valid/invalid indicating circuit which outputs data indicating whether or not said read-out data output to said output circuit is valid, to a peripheral circuit of said memory in every k bits, as one unit.
In the second aspect of the present invention, the data at an address indicated by said reading pointer is constantly output to said output circuit.
In the third aspect of the present invention, at each time when read-out data is output to said output circuit, said valid/invalid indicating circuit outputs a flag signal that indicates whether or not said read-out data is valid, and also outputs one flag signal in every k bits.
In the fourth aspect of the present invention, said flag signal comprising N bits.
In the fifth aspect of the present invention, the value of said reading pointer being incrementable only when all bits of said flag signal that is output from said valid/invalid indicating circuit indicate to be valid.
The method for controlling a FIFO memory device according to the present invention is used for data transfer between data processing apparatuses having different data bus widths from each other, and which comprising a writing pointer that indicates a data writing address, a reading pointer that indicates a data reading address, an input circuit of said device with a data bus width of M×k bits (where M and k are integers greater than 1), and an output circuit of said device with a data bus width of N×k bits (where N is an integer greater than 1, but being different from said M) that outputs read-out data from a memory provided within said FIFO memory device, wherein data at an address indicated by said reading pointer being constantly output to said output circuit, and further wherein a valid/invalid indicating circuit indicating whether or not said read-out data output to said output circuit is valid, said data output from said valid/invalid indicating circuit is output to a peripheral circuit of said FIFO memory device in every k bits as one unit.
Because in a FIFO memory device according to the present invention, for use in data transfer between data processing apparatuses having different data bus widths, has a writing pointer that indicates a data writing address, a reading pointer that indicates a data reading address, the data at an address indicated by the reading pointer being constantly output, it is possible to use this FIFO memory device for data transfer between data processing apparatuses having different data bus widths and enable high-speed transfer of data.
Additionally, the present invention prevents such problems as skipped writing and double reading of data without the need to use bus arbitration as was done in the past.


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