Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-17
2004-07-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06759708
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor manufacture and, more particularly, to polysilicon structures in a stacked gate region of a semiconductor device, such as for example, a flash memory device.
As computers become increasingly complex, the need for improved memory storage, and in particular, the need for an increased number of memory cells per unit area, increases. At the same time, there is a continuing drive to minimize the size of computers and memory devices. Accordingly, it is a goal of memory device fabrication to increase the number of memory cells per unit area or wafer area.
A conventional non-volatile semiconductor memory device in which contents are electrically programmable and simultaneously erased by one operation is a flash memory device. Flash memory allows for blocks of memory cells to be erased in one operation. Flash memory devices have the characteristics of low power and fast operation making them ideal for portable devices. Flash memory is commonly used in portable devices such as laptop or notebook computers, digital audio players and personal digital assistant (PDA) devices.
In flash memory, a charged floating gate is one logic state, typically represented by the binary digit 1, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 0. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example.
An important parameter for a flash memory cell is the capacitive coupling of the memory cell. It is difficult to reduce the size or scale down the memory cell while maintaining a desired or required capacitive coupling. This parameter can be a significant factor in the drive to reduce memory cell size. Accordingly, there is a need for a memory cell production scheme directed to reducing the size of a memory cell while maintaining or improving the capacitive coupling of the memory cell.
SUMMARY OF THE INVENTION
This need is met by the present invention, wherein a stacked gate region of a memory cell is disclosed. The flash memory device includes a substrate, at least one trench, an oxide layer, at least one floating gate and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate and over the oxide layer. Other methods and devices are disclosed.
The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.
According to one embodiment of the invention, a stacked gate region of a memory cell is disclosed having a substrate, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate is formed over the tunnel oxide layer. The at least one polysilicon wing is formed adjacent to the at least one floating gate layer and over a portion of the field oxide region.
According to another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, at least one trench, field oxide, a tunnel oxide layer, at least one floating gate and at least one polysilicon ear. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The field oxide is deposited in the at least one trench and extends above an upper surface of the substrate. The tunnel oxide layer is formed over at least a portion of the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon ear is formed on the at least one floating gate layer and adjacent to the field oxide.
According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, at least one trench, a tunnel oxide layer, at least one floating gate layer, field oxide and at least on polysilicon ear. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate. The tunnel oxide layer is formed over at least a portion of the substrate. The at least one floating gate layer is formed over the oxide layer. The field oxide is deposited in the at least one trench. The at least one polysilicon ear is formed on the at least one floating gate layer.
According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon wings. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon wings are located adjacent to opposite ends of the floating gate layer, co-planer with the floating gate layer and over a portion of corresponding ones of the field oxide regions.
According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon ears. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon ears are formed adjacent to corresponding ones of the field oxide regions on the floating gate layer and projecting perpendicular to an upper surface of the floating gate layer.
According to yet another embodiment of the invention, a stacked gate region of a memory cell is disclosed. The stacked gate region includes a substrate, a plurality of trenches, a tunnel oxide layer, at least one floating gate layer, field oxide regions and a pair of polysilicon ears. The substrate has at least one semiconductor layer. The plurality of trenches are formed in the substrate. The respective field oxide regions are formed in the trenches. The tunnel oxide layer is formed over the substrate. The floating gate layer is formed over the tunnel oxide layer. The pair of polysilicon ears are formed adjacent to the floating gate layer.
According to yet another embodiment of the invention, a memory cell is disclosed. The memory cell includes a substrate, a source, a drain, at least one trench, a field oxide region, a tunnel oxide layer, at least one floating gate layer, at least one polysilicon wing, a dielectric layer and a control gate. The substrate has at least one semiconductor layer. The source is formed in the substrate. The drain is formed in the substrate. The at least one trench is formed in the substrate. The field oxide region is formed in the trench. The tunnel oxide layer is formed over the substrate. The at least one floating gate layer is formed over the tunnel oxide layer. The at least one polysilicon wing is formed adja
Hurley Kelly T.
Wolstenholme Graham
Dinsmore & Shohl LLP
Flynn Nathan J.
Micro)n Technology, Inc.
Quinto Kevin
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