Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-16
2004-01-13
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06678873
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of designing a semiconductor integrated circuit by using a database in which existing properties such as IPs are stored.
In generating a new semiconductor integrated circuit device (an LSI, a system LSI, or a circuit) by using IPs as existing properties or partly modifying an existing semiconductor integrated circuit device, a selection of IPs (such as chips) to construct such a system has been executed conventionally during the design stage by depending on the experience of a designer who manually builds up functions in the respective IPs.
A high degree of skill is particularly required of the designer in the case of integrating IPs which are different in parameters such as circuit scale, memory capacity, number of pins, and clock system or in synchronous
on-synchronous operating modes, reconstructing or generating a system having a plurality of processors, or using some of IPs.
However, as a semiconductor integrated circuit device to be designed has been increased in scale in recent years, discrepancies in a plurality of parameters have been observed among an enormous number of elements composing the semiconductor integrated circuit. When IPs as the existing design resources are reused, it is particularly difficult to effectively use the IPs or some of the IPs by depending only on the experience of the designer due to the discrepancies in parameters and the like. As a result, a situation where the design period is increased significantly or design itself is impossible.
SUMMARY OF THE INVENTION
The present invention has been achieved by focusing attention on the fact that the cause of the foregoing difficulties encountered in the conventional design of a semiconductor integrated circuit device is lack of proper means for dividing each IP into functions and analyzing and grouping the functions. It is therefore an object of the present invention to design a semiconductor integrated circuit device in consideration of different parameters and the like after analyzing the function of each IP and thereby reducing a design period through automated design and improve the quality of the designed semiconductor integrated circuit device.
A first method of designing a semiconductor integrated circuit device is a method of designing a semiconductor integrated circuit device by using a database storing therein data on a plurality of circuits having different parameters, the method comprising the steps of: (a) inputting specifications required of the semiconductor integrated circuit device; (b) inputting data on the plurality of circuits stored in the database and automatically analyzing the parameters of the circuits; and (c) automatically designing the semiconductor integrated circuit device in accordance with a result of the analysis to satisfy the required specifications.
The method allows a plurality of circuits containing different parameters to be automatically integrated into a single semiconductor integrated circuit device, while satisfying the required specifications. This allows a reduction in design period and an improvement in the quality of the designed semiconductor integrated circuit device even if it is on a large scale.
The parameters are scales of the plurality of circuits, the step (a) includes inputting constraints on a circuit area or a number of gates of the semiconductor integrated circuit device to be designed, and the step (b) includes analyzing a combination of circuits to be embedded in the semiconductor integrated circuit device, while holding the circuit area or number of gates of the semiconductor integrated circuit device within the constraints, whereby the circuit area of the designed integrated circuit device is minimized.
The step (b) includes analyzing sharability of a pad between the circuits. This allows a reduction in circuit area through the sharing of the pad.
The parameters are types or capacities of memories of the plurality of circuits, the step (a) includes inputting types of memories of the semiconductor integrated circuit device to be designed and constraints on capacities thereof, and the step (b) includes analyzing an optimum combination of memories according to sharing of an external memory between the circuits and to sharability or divisibility of the memories between the circuits.
This minimizes the memory capacity.
The parameters are numbers of pins of the plurality of circuits, the step (a) includes inputting constraints on a number of pins of each of circuits of the semiconductor integrated circuit device to be designed, and the step (b) includes analyzing an optimum combination; of circuits, while holding the number of pins of each of the circuits within the constraints.
This allows design considering constraints on the number of pins.
The step (b) includes analyzing the optimum combination of circuits also in consideration of types of the pins of each of the circuits. This allows design considering the compatibility of the attributes of the pins as well.
The parameters are clock frequencies of the plurality of circuits, the step (a) includes inputting a clock frequency in each of circuits of the semiconductor integrated circuit device to be designed, and the step (b) includes analyzing an optimum combination of circuits such that the operating frequencies of the circuits match the clock frequency inputted in the step (a).
This allows the semiconductor integrated circuit device to be designed, while causing a large number of circuits to operate smoothly with the required clock frequency.
The step (b) includes performing the analysis for sharing of a clock generator between the circuits and for optimization of clock lines. This further improves the quality of the designed semiconductor integrated circuit device.
A second method of designing a semiconductor integrated circuit device is a method of designing a semiconductor integrated circuit by using a database storing therein data on at least respective upper-limit operating frequencies of a plurality of circuits having different operating frequencies, the method comprising the step of: analyzing the operating frequencies and upper-limit operating frequencies of the plurality of circuits stored in the database and optimizing or reconstructing the plurality of circuits.
The method allows easy designing of a semiconductor integrated circuit device into which a plurality of circuit operating at different frequencies have been incorporated.
A third method of designing a semiconductor integrated circuit device is a method of designing a semiconductor integrated circuit device by using a database storing therein data on at least upper-limit operating frequencies of a plurality of circuits having different operating frequencies, the method comprising the steps of: (a) inputting specifications required of a clock of the semiconductor integrated circuit device; (b) fetching data on the plurality of circuits in the database and analyzing a possibility of a trade-off between the upper-limit operating frequencies of the circuits and the specifications required of the clock; and (c) displaying whether or not the semiconductor integrated circuit can be designed depending on a result of the analysis.
The method allows designing of a semiconductor integrated circuit device in consideration of the upper-limit operating frequencies of the plurality of circuits, while causing the operations of the plurality of circuits to satisfy the required specifications.
The step (b) includes performing the analysis in consideration of a possibility of sharing a clock system between the circuits. This renders the clock system in the designed semiconductor integrated circuit device as simple as possible.
Preferably, the method further comprises, if it is judged in the step (c) that the semiconductor integrated circuit device cannot be designed, the step of: (d) generating, for those of the plurality of circuits which do not satisfy the specifications required of the clock inputted in the step (a), additional circuits for causing the circuits to sat
Fujimoto Hitoshi
Ishida Kenichi
Kohashi Yasuo
Matsuo Masatoshi
Moriiwa Tosihiro
Bowers Brandon
Garbowski Leigh M.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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