Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-12-20
2004-04-20
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S142000, C438S279000, C438S302000, C438S689000
Reexamination Certificate
active
06723623
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming implant regions. In particular aspects, the invention pertains to methods of forming pocket implant regions and/or an L
DD
region for a bitline contact source/drain region shared between a pair of adjacent transistor gates.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) arrays are commonly utilized semiconductor constructions. The arrays typically comprise large numbers of individual DRAM cells, with each cell typically containing a capacitor for data storage. Each capacitor is electrically connected to a source/drain region of a transistor, with the transistor gate typically being part of a wordline. A bitline is electrically connected to another source/drain region of the transistor, and the transistor gatedly connects the bitline with the capacitor.
It is common for a pair of adjacent DRAM cells to share a bitline connection. A transistor associated with one DRAM cell has a source/drain region which overlaps the source/drain region of an adjacent transistor associated with a second DRAM cell. The overlapping source/drain region is in electrical connection with a bitline contact, and accordingly the bitline contact is shared between the adjacent DRAM cells.
Exemplary processing for forming a pair of adjacent DRAM cells is described with reference to
FIGS. 1-6
.
Referring initially to
FIG. 1
, a semiconductor construction
10
is illustrated at a preliminary processing stage. Construction
10
comprises a substrate
12
having an insulative material
14
formed thereover. Substrate
12
can comprise, consist essentially of, or consist of a single crystal semiconductive material (such as, for example, monocrystalline silicon) lightly doped with an appropriate dopant (such as, for example, a p-type dopant). For instance, substrate
12
can be a monocrystalline silicon wafer background doped with p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone, or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also to aid in interpretation of this disclosure and the claims that follow, the terms “insulative” and “conductive” are to be understood to refer to electrically insulative and electrically conductive materials, respectively.
Insulative material
14
can comprise, for example, silicon dioxide, and can ultimately be utilized to form a so-called pad oxide layer for transistor gates.
A conductive material
16
is formed over insulative layer
14
. Conductive material
16
can comprise, consist essentially of, or consist of, for example, conductively-doped silicon, such as, for example, conductively-doped polycrystalline silicon. If conductive material
16
comprises conductively-doped silicon, the dopant can be either n-type or p-type dopant, and in typical applications of forming DRAM arrays will be n-type dopant.
Conductive layers
18
and
20
are formed over conductive material
16
. Conductive layers
18
and
20
can comprise, consist essentially of, or consist of metal and/or metal compounds. In an exemplary construction, layer
18
will comprise, consist essentially of, or consist of tungsten nitride; and layer
20
will comprise, consist essentially of, or consist of tungsten.
An insulative cap
22
is formed over conductive material
20
. Insulative cap
22
can comprise any suitable electrically insulative material, including, for example, silicon nitride; and in particular applications will consist of silicon nitride.
Layers
14
,
16
,
18
,
20
and
22
can collectively be referred to as a gate stack
24
. It is noted that the shown gate stack is but one exemplary type of gate stack and that numerous other types of gate stacks can be utilized in forming transistor constructions. For instance, insulative material
14
can optionally not be considered part of the gate stack. Alternatively, insulative material
14
can be considered part of the gate stack and can comprise several layers of insulative materials. Also, even though three separate conductive layers are shown (
16
,
18
and
20
) it is to be understood that more than three separate conductive layers can be utilized, or in other applications less than three separate conductive layers can be utilized. In the shown construction, typical thicknesses of layers
14
,
16
,
18
,
20
and
22
are about 70 Angstroms, about 500 Angstroms, about 100 Angstroms, about 200 Angstroms, and about 1500 Angstroms, respectively. The drawings are utilized to illustrate respective orientations of the shown layers, and are diagrammatic illustrations only. Accordingly, respective thicknesses of the various layers are not shown to scale.
A patterned mask
26
is formed over insulative material
22
. Mask
26
can comprise, for example, photoresist, and is utilized to define locations of transistor gates. If mask
26
comprises photoresist, such can be patterned utilizing photolithographic methods.
Referring to
FIG. 2
, a pattern is transferred from mask
26
(
FIG. 1
) to underlying layers
16
,
18
,
20
and
22
to define a pair of partially-formed transistor gates
30
and
32
; and the mask is subsequently removed. The transfer of a pattern from the mask to the underlying layers can be accomplished utilizing a suitable etch. It is noted that the etch has only proceeded partially through conductive material
16
, and thus leaves an unetched portion of material
16
remaining over layer
14
, in addition to forming an etched portion of material
16
.
The partially-formed transistor gates
30
and
32
have sidewalls
34
and
36
, respectively. An opposing pair of sidewalls is associated with each transistor gate.
Referring to
FIG. 3
, an insulative material
40
is formed over the unetched portion of conductive material
16
, as well as along the sidewalls
34
and
36
of partially-formed transistor gates
30
and
32
. Additionally, insulative material
40
extends over tops of the partially-formed transistor gates
30
and
32
. Insulative material
40
can comprise any suitable material, and, in exemplary applications, comprises, consists essentially of, or consists of silicon nitride.
Referring to
FIG. 4
, layer
40
is anisotropically etched to form sidewall spacers
42
and
44
along the sidewalls
34
and
36
, respectively. After formation of spacers
42
and
44
, an etch is utilized to extend the opening through the remaining portion of conductive material
16
, as well as through insulative material
14
. The etch completes formation of transistor gates
30
and
32
, and exposes a surface of substrate
12
between the transistor gates. It is to be understood, however, that in other processing (not shown) the opening can be extended through the remaining portion of conductive material
16
, but not through insulative material
14
; and accordingly material
14
can be left over an upper surface of substrate
12
after the etch.
In applications in which insulative cap
22
consists of silicon nitride, sidewall spacers
42
and
44
consist of silicon nitride, and in which conductive material
16
consists of conductively-doped silicon, a suitable etch for conductive material
16
is an etch selective for conductively-doped silicon relative to silicon nitride.
After etching through the remaining portion of conductive material
16
, source/drain regions
46
,
48
and
50
can be formed proximate the transistor gates utilizing an appropriate implant. For instance, the source/drain regions can be heavily-doped n-type regions, and accordingly can be formed utilizing a suitable implant of n-type dopant. As shown, the regions are self-aligned relative to tr
Micro)n Technology, Inc.
Sarkar Asok Kumar
Wells St. John P.S.
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