Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-15
2004-05-25
Hoang, Huan (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06740917
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor memory having a multiplicity of memory cells, which, in a first direction parallel to the surface of a semiconductor substrate, are connected in rows to word lines and, in a second direction parallel to the surface of the semiconductor substrate, are connected in rows to bit lines. The invention furthermore relates to a method for fabricating an integrated semiconductor memory.
Integrated semiconductor memories have a memory cell array in which memory cells are disposed in the form of a matrix on the surface of a semiconductor substrate. Each memory cell has at least one transistor by which the respective memory cell can be driven by mutually crossing lines by which the memory state of the memory cell can be read or altered.
Word lines and bit lines are provided for the electrical driving of the selection transistors. In the case of a MOSFET (metal oxide semiconductor field-effect transistor) as the selection transistor, the gate of the transistor is connected to the word line and the source is connected to the bit line. Word lines and bit lines run parallel to the plane surface of the semiconductor substrate and perpendicularly to one another, i.e., they mutually cross one another. The selection transistors of the memory cells are situated at the crossover points of the lines.
In every semiconductor memory, attempts are made to keep the area taken up by an individual memory cell on the semiconductor substrate as small as possible to allow storage of as much information as possible on the substrate area. The area requirement of a memory cell is prescribed firstly by the complexity of the individual memory cell. A memory cell contains at least one selection transistor and a storage capacitor.
The area requirement is furthermore prescribed by the structure width with which microelectronic structures are produced by lithographic exposure processes on the substrate. The structure width is the minimum width of a microelectronic structure, i.e., a trench or a web, which can be reliably fabricated with a prescribed fabrication technology. Because microelectronic structures are formed using lithographically fabricated masks, the area requirement of a memory cell can be specified in numbers of squares with an edge length that corresponds to the structure width. The minimum area of a structure element is, thus, a square having the size of 1 f
2
(f represents the structure width in this case).
Finally, the area requirement is determined by the complexity and the construction of the memory cell itself. The area requirement can be optimized through the type of configuration of the selection transistor, of the storage capacitor, and, if appropriate, of further transistors or other constituent parts of the memory cell.
Today's memory cells require at least an area of 8 f
2
on a semiconductor substrate. Such an area is necessary even in the case of a transistor that has only one selection transistor and a storage capacitor because it is necessary to comply with a certain minimum distance from adjacent memory cells, the minimum distance likewise corresponding to the structure width.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor memory and fabrication method that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that further reduces the area requirement of a memory cell.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated semiconductor memory, including a semiconductor substrate having a surface, bit lines, word lines, memory cells connected, in a first direction parallel to the surface of the semiconductor substrate, in rows to the word lines and connected, in a second direction parallel to the surface, in rows to the bit lines, two of respective one of word lines and bit lines being disposed as line pairs, each of the line pairs having a buried line running in the semiconductor substrate and an upper line disposed above the buried line, and the upper line of a given line pair connected to one of the memory cells and the lower bit line of the given line pair being connected to another different one of the memory cells.
With the objects of the invention in view, there is also provided an integrated semiconductor memory, including a semiconductor substrate having a surface, bit lines, respective pairs of the bit lines being disposed as bit line pairs, word lines, respective pairs of the word lines being disposed as word line pairs, memory cells connected, in a first direction parallel to the surface of the semiconductor substrate, in rows to the word lines and connected, in a second direction parallel to the surface, in rows to the bit lines, at least one of the word line pairs and the bit line pairs having a buried line running in the semiconductor substrate and an upper line disposed above the buried line, the upper line being connected to one of the memory cells, and the buried line being connected to another different one of the memory cells.
The integrated semiconductor memory by virtue of the fact that in each case two word lines or in each case two bit lines are formed as line pairs including two lines disposed one above the other, each line pair having a buried line running in the semiconductor substrate and an upper line disposed above the buried line and in that in each case different memory cells are connected to the upper line of a line pair then to the lower bit line of the same line pair.
According to the invention, the leads for the selection transistors for the memory cells are not only disposed along the surface of the semiconductor substrate in the form of a matrix, but layering into the substrate is additionally effected in the case of at least one type of leads—the word lines or the bit lines. In such a case, these layered lines are disposed in the form of line pairs in the substrate, the lower line of which runs in a manner buried in the substrate and is insulated from the overlying line by an insulating layer. The two lines of a line pair are disposed one above the other, i.e., one vertically above the other, for example, in a common trench one above the other or in the same region of the base area of the semiconductor substrate.
As a result, the memory cells can be disposed, at least in one direction, with up to double the memory cell density on the semiconductor substrate. Along the paired lines, the memory cells are alternately connected to the upper line and the buried line, thereby enabling all the memory cells to be contact-connected. The contact connection can also be effected on different sides of the interconnects, for example, toward the right proceeding from the buried lines and toward the left proceeding from the upper lines. The present invention's configuration of the lines to form line pairs with lines lying one above the other in the depth enables new configurations and construction of memory cells.
In accordance with another feature of the invention, the bit lines are disposed as buried line pairs and the word lines are disposed laterally next to one another. Such a configuration is advantageous if vertical transistors have to be connected to the bit lines. In such a case, source and drain are situated one above the other so that one of the electrodes can be connected to the buried bit line and the other to the upper bit line. Particularly when the source connections of adjacent selection transistors are disposed alternately above and below the gate connection, the bit line pair according to the invention enables contact connection in two different substrate depths.
Preferably, the word lines cross the line pairs of the bit lines in a middle substrate depth between the two bit lines of a line pair. In such an embodiment, the word lines can still be disposed very near the surface in the semiconductor substrate. A bit line, a word line, and a further bit
Greenberg Laurence A.
Hoang Huan
Hoang Quoc
Infineon - Technologies AG
Locher Ralph E.
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