Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-08-12
2004-09-07
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S302000, C438S525000, C438S531000, C438S944000
Reexamination Certificate
active
06787406
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and, more particularly, to systems and methods for creating dense n-channel and p-channel fins for metal-oxide semiconductor field-effect transistor (MOSFET) devices using shadow implanting techniques.
BACKGROUND OF THE INVENTION
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability, and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
Double-gate MOSFETs represent devices that are candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, the use of two gates to control the channel significantly suppresses short-channel effects. A FinFET is a double-gate structure that includes a channel formed in a vertical fin. Although a double-gate structure, the FinFET is similar to existing planar MOSFETs in layout and fabrication techniques. The FinFET also provides a range of channel lengths, CMOS compatibility, and large packing density compared to other double-gate structures.
SUMMARY OF THE INVENTION
Implementations consistent with the principles of the invention provide n-channel and p-channel fins for MOSFET devices that are tightly spaced and formed using shadowed implant techniques.
In one aspect consistent with the principles of the invention, a method for doping fins of a semiconductor device that includes a substrate is provided. The method includes forming fin strictures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.
According to another aspect, a semiconductor device includes fins formed adjacent to one another, where a distance between side surfaces of the fins is approximately 200 Å. The device further includes a source region formed at one end of the fins, a drain region formed at an opposite end of the fins, and at least one gate.
According to a further aspect, a method for doping fins of a semiconductor device that includes a substrate is provided. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap portion formed on a fin portion. The method also includes performing a first tilt angle implant process to dope a first one of the fin portions with n-type impurities from a first direction and performing a second tilt angle implant process to dope a second one of the fin portions with p-type impurities from a second direction. The method further includes performing a third tilt angle implant process to further dope the first one of the fin portions with n-type impurities from the second direction and performing a fourth tilt angle implant process to further dope the second one of the fin portions with p-type impurities from the first direction.
REFERENCES:
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” I999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer finFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. application Ser. No. 10/728,910, filed Dec. 8, 2003, entitled: “SRAM Formation Using Shadow Implantation”, 15 page specification, 13 sheets of drawings.
Ahmed Shibly S.
Hill Wiley Eugene
Wang Haihong
Yu Bin
Advanced Micro Devices , Inc.
Coleman W. David
Harrity & Snyder LLP
Pham Thanh
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