Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2003-12-15
2004-09-21
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S154000, C365S230080
Reexamination Certificate
active
06795368
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit-device, and to a technology effective for application to a large-scale integrated circuit provided with a memory circuit which performs a high-speed read operation.
One example of a static memory cell provided with a write port and a read port has been disclosed in Unexamined Patent Publication No. Hei 8(1996)-129891 (corresponding U.S. Pat. No. 5,592,414).
SUMMARY OF THE INVENTION
While the above-described memory cell having the read-only port is suited for a high-speed operation, a differential circuit is generally used as an amplifier circuit for sensing a read signal thereof. With micro-fabrication of each device according to semiconductor technology developments, a reduction in source or power supply voltage has been put forward. However, an improvement in offset voltage of a differential sense amplifier is not capable of coping with the reduction in the power supply voltage. It is expected that it will be advantageous to take a configuration for amplifying the read signal by means of an inverter circuit.
Since, however, an inverter-amplified circuit is not operated until the potential at each bit line exceeds a logical threshold value of an inverter, a circuit delay is large. Substituting a dynamic circuit for the inverter yields an improvement in circuit delay. However, the mere application of the dynamic circuit to an SRAM having a hierarchical bit line structure will cause a high possibility that a timing hazard of an internal circuit, i.e., a malfunction will be produced with respect to variations in manufacture. Or an excessive margin is needed to avoid the malfunction, thus causing a possibility that frequency performance of the circuit will be rate-controlled.
An object of the present invention is to provide a semiconductor integrated circuit device equipped with a memory circuit, which enables speeding up and facilitation of timing settings. Another object of the present invention is to provide a novel semiconductor integrated circuit device provided with a high-speed memory and a large storage capacity memory circuit. The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: There are provided first amplifier circuits; which include first MOSFETs of first conductivity type which have gates provided for a plurality of bit lines to which memory cells are respectively connected and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and there is also provided a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.
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Higeta Keiichi
Iwahashi Satoshi
Nakahara Shigeru
Suzuki Takeshi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Le Vu A.
Reed Smith LLP
Renesas Technology Corp.
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