Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-21
2004-03-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S042000, C365S201000
Reexamination Certificate
active
06711705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC) and a method of analyzing a relief or repair of failure cell or cells in a memory, which includes the steps of counting the number of failure memory cells of a semiconductor memory tested by this memory testing apparatus and determining whether or not a repair of the tested semiconductor memory is possible. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.) More particularly, the present invention relates to a method of analyzing a repair of failure cell or cells in a memory, which includes the step of specifying an address of a failure memory cell in a memory of redundancy structure in a short time and a memory testing apparatus having a failure relief analyzer using this analyzing method.
2. Description of the Related Art
Recently, an IC memory is being increased in its memory capacity and miniaturized in its size, and accompanied therewith, a defect rate in IC memories have been increased. In order to decrease the defect rate, in other words, in order to prevent the yield of IC memories from being lowered, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit in this technical field). The IC memories of this kind each having substitute or alternative memory cells (hereinafter referred to as spare line) is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 5
is a block diagram showing, in outline, a configuration of the general memory testing apparatus having a failure relief analyzer, which has conventionally been used. This memory testing apparatus TES comprises, roughly speaking, a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logical comparator
115
, a driver
116
, an analog level comparator (hereinafter referred to as comparator)
117
, a failure analysis memory
118
, a failure relief analyzer
120
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
and a device power source
123
. Further, in the following description, a case that the memory testing apparatus will test IC memories will be described. In case of testing various kinds of semiconductor memories other than IC memories by the memory testing apparatus, however, they will be tested in similar manner.
The main controller
111
is generally constituted by a computer system, in which a test program PM created by a user (programmer) is stored in advance, and the entire memory testing apparatus is controlled in accordance with the test program PM. The main controller
111
is connected, via a tester bus BUS, to the pattern generator
112
, the timing generator
113
, the failure analysis memory
118
, the failure relief analyzer
120
and the like. Although not shown, the logical amplitude reference voltage source
121
, the comparison reference voltage source
122
, and the device power source
123
are also connected to the main controller
111
.
An IC memory to be tested (IC memory under test, generally called MUT)
119
is mounted on a IC socket of a test head (not shown) constructed separately from the memory testing apparatus proper. Usually, a member called a performance board is mounted on the upper portion of the test head, and a predetermined number of IC sockets are mounted on the performance board. Accordingly, the IC memory under test
119
is mounted on associated one of the IC sockets. In addition, a printed board called pin card in this technical field is accommodated inside the test head. Usually, a circuit including the driver
116
and the comparator
117
of the memory testing apparatus TES is formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and handling apparatus called handler in this technical field, and is electrically connected to the memory testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
First of all, before the test of an IC memory is started, various kinds of data are set by the main controller
111
. After the various kinds of data have been set, the test of the IC memory is started. When the main controller
111
gives a test starting instruction or command to the pattern generator
112
, the pattern generator
112
starts to generate a pattern. The pattern generator
112
supplies test pattern data to the waveform formatter
114
in accordance with the test program PM. On the other hand, the timing generator
113
generates a timing signal (clock pulses) for controlling operation timings of the waveform formatter
114
, the logical comparator
115
and the like.
The waveform formatter
114
converts the test pattern data supplied from the pattern generator
112
into a test pattern signal having a real waveform. This test pattern signal is applied to the IC memory under test (hereinafter referred to as memory under test)
119
via the driver
116
that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source
121
. The test pattern signal is stored in a memory cell of the memory under test
119
having an address specified by an address signal, and the storage content is read out therefrom in a read cycle executed later.
A response signal read out from the memory under test
119
is compared with a reference voltage supplied from the comparison reference voltage source
122
in the comparator
117
, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator
115
, where the response signal is compared with an expected value pattern signal outputted from the pattern generator
112
, and whether or not the memory under test
119
has outputted a normal response signal is determined.
If the response signal does not coincide with the expected value pattern signal, the logical comparator
115
determines that the memory cell having an address of the memory under test
119
from which the response signal has been read out is defective (failure), and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a writing of a failure data (generally logical “1” signal) in the failure analysis memory
118
applied to a data input terminal thereof is enabled, and the failure data is stored in an address of the failure analysis memory
118
specified by an address signal being supplied to the failure analysis memory
118
at that time.
The failure analysis memory
118
has its operating rate or speed and its memory capacity equivalent to those of the memory under test
119
, and the same address signal as the address signal applied to the memory under test
119
is also applied to this failure analysis memory
118
. In addition, the failure analysis memory
118
is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory
118
has data of logical “0s” written in all of the addresses thereof. Every time a failure signal indicating that the anti-coincidence is generated from the logical comparator
115
during a testing of the memory under test
119
, a failure data of logical “1” indicating the failure of a memory cell is written in the same address of the failure analysis memory
118
as that of the m
Advantest Corporation
De'cady Albert
Gallagher & Lathrop
Gandhi Dipakkumar
Lathrop, Esq. David N.
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