Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-20
2004-03-02
Tsai, H. Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C438S003000, C438S250000
Reexamination Certificate
active
06700147
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-255136, filed on Aug. 30, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
The nonvolatile memory element having the ferroelectric capacitor, which is called FeRAM or FRAM, is put on the market as the semiconductor memory. This nonvolatile memory element has features of a high-speed operation; low power consumption, and the large number of writing times, and its future development is anticipated.
As the capacitor formed in the memory cell area of such nonvolatile memory element, the planar type and the stacked type are known.
The planar capacitor has such a structure that the first wiring formed on the insulating layer, which covers the capacitor, is connected to the upper electrode via the first contact hole and the second wiring formed on the insulating film is connected to the lower electrode via the second contact hole.
The stacked capacitor has such a structure that the lower electrode is directly formed on the conductive plug formed in the insulating layer as the underlying layer of the capacitor. However, since the ferroelectric material and the lower electrode material constituting the capacitor are grown to take over the orientation of the underlying layer, the underlying layer must be made flat and formed of single material. Also, since the oxygen is indispensable to form the ferroelectric material and the lower electrode material is ready to transmit the oxygen, the conductive plug is oxidized to cause the defective contact readily.
Therefore, currently the planar capacitor is employed in most of FeRAMs that are available on the market.
The memory cell having the planar capacitor has a structure showing in
FIG. 1
to
FIG. 3
, for example.
FIG. 1
is a plan view showing a part of the memory cell area of FeRAM, and insulating layers except the element isolation insulating layer are omitted from the illustration.
FIG. 2
is a sectional view taken along a I—I line in
FIG. 1
, and
FIG. 3
is a sectional view taken along a II—II line in FIG.
1
.
In
FIG. 1
, a well region
103
that is surrounded by an element isolation insulating layer
102
is formed on a silicon substrate
101
. Then, MOS transistors
107
a
,
107
b
having a sectional structure shown in
FIG. 2
are formed in the well region
103
. Then, a planar capacitor
100
having a sectional structure shown in FIG.
2
and
FIG. 3
is formed on the side of the well region
103
.
In
FIG. 2
, two gate electrodes
105
a
,
105
b
are formed over the well region
103
, which is surrounded by the element isolation insulating layer
102
, of the silicon substrate
101
via a gate insulating layer
104
. Also, impurity diffusion regions
106
a
,
106
b
.
106
c
having the LDD structure are formed in the silicon substrate
101
on both sides of the gate electrodes
105
a
,
105
b
. The first MOS transistor
107
a
consists of one gate, electrode
105
a
, the impurity diffusion regions
106
a
,
106
b
, etc. Also, the second MOS transistor
107
b
consists of the other gate electrode
105
b
, the impurity diffusion regions
106
b
,
106
c
, etc.
The element isolation insulating layer
102
and the MOS transistors
107
a
,
107
b
are covered with first and second insulating layers
108
,
109
. An upper surface of the second insulating layer
109
is planarized by the CMP (Chemical Mechanical Polishing) method, and the ferroelectric capacitor
100
is formed on the upper surface.
The ferroelectric capacitor
100
has a lower electrode
100
a
having a contact area, a ferroelectric layer
100
b
, and an upper electrode
100
c
. Then, a third insulating film
110
is formed on the capacitor
100
and the second insulating layer
109
. The lower electrode
100
a
is formed by patterning a platinum layer. Also, the ferroelectric layer
100
b
is formed by patterning a PZT layer, for example. Then, the upper electrode
100
c
is formed by patterning an iridium oxide layer, for example.
In the first to third insulating layers
108
to
110
, a first contact hole
110
b
is formed on the impurity diffusion region
106
between two gate electrodes
104
a
,
104
b
and also second and third contact holes
110
a
,
100
c
are formed on the impurity diffusion regions
106
a
,
106
c
located near both ends of the well region
103
respectively. Also, as shown in
FIG. 3
, a fourth contact hole
110
d
is formed on the contact area of the lower electrode
100
a.
First to fourth conductive plugs
111
a
to
111
d
made of an adhesive layer and a tungsten layer respectively are formed in the first to fourth contact holes
110
a
to
110
d
. Also, a fifth contact hole
112
is formed on the upper electrode
100
c
of the capacitor
100
.
A first wiring
120
a
, which is connected to an upper surface of the first conductive plug
111
a
and is connected to the upper electrode
100
c
via the fifth contact hole
112
, is formed on the third insulating layer
110
. Also, a second wiring
120
c
, which is connected to an upper surface of the third conductive plug
111
c
and is connected to another upper electrode
100
c
via another fifth contact hole
112
, is formed on the third insulating layer
110
. Also, a conductive pad
120
b
is formed on the second conductive plug
111
b
and the neighboring third insulating layer
110
.
In addition, as shown in
FIG. 3
, a third wiring
120
d
, which is connected to an upper surface of the contact area of the lower electrode
100
a
via the fourth conductive plug
111
d
, is formed on the third insulating layer
110
.
A fourth insulating layer
121
is formed on the first, second, and third wirings
120
a
,
120
c
,
120
d
, the conductive pad
120
b
, and the third insulating layer
110
. A sixth contact hole
121
a
is formed in the fourth insulating layer
121
on the conductive pad
120
b
. A bit-line conductive plug
122
is formed in the sixth contact hole
121
a
. Also, a bit line
123
that is connected to the bit-line conductive plug
122
is formed on the fourth insulating layer
121
.
By the way, in the above planar capacitor
100
, as shown in
FIG. 3
, the contact area of the lower electrode
100
a
of the capacitor
100
is exposed from the ferroelectric layer
100
b
before the third insulating layer
110
is formed.
If the reducing gas is employed as the reaction gas when the fourth conductive plug
111
d
is to be formed on the lower electrode
100
a
, such reaction gas is supplied to the lower electrode
100
a
of the capacitor
100
via the contact hole
110
d
and then is moved along the lower electrode
100
a
to reduce the ferroelectric layer
100
b
. Therefore, the deterioration of the characteristics of the capacitor
100
that is formed in the area that is located in vicinity of the fourth conductive plug
111
d
is caused. Also, since the lower electrode
100
a
made of platinum is exposed from the ferroelectric layer
100
b
in the contact area to the fourth conductive plug
111
d
, the characteristics of the capacitor
100
located near the contact area are ready to deteriorate because of the catalytic action of the platinum.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of suppressing deterioration of a capacitor in an area located in vicinity of a contact portion between a lower electrode and a wiring, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first insulating layer formed on a semiconductor substrate; a conductive pattern formed on the first insulating layer; a second insulating layer for covering the conductive pattern; a first hole formed in the second insulating layer o
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Tsai H. Jey
LandOfFree
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