Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-12-27
2004-03-16
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S749000, C438S750000, C438S753000, C438S754000
Reexamination Certificate
active
06706642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for fabricating semiconductor capacitors, and more particularly to a method for fabricating semiconductor capacitors, which enables the capacitance of the capacitors to be increased.
2. Description of the Prior Art
As the integration density of a semiconductor device fabricated on a semiconductor substrate is increased, an area that can be occupied by a capacitor cell for data storage in a DRAM device is also reduced. Thus, the capacitance of the capacitor fabricated on a semiconductor wafer is decreased with a reduction in design rule.
However, in a DRAM capacitor cell, in order to ensure strong resistance against soft error caused by an alpha particle and to prevent malfunction caused by noise, there is required a capacitor cell having sufficient capacitance.
Namely, even in the case of a giga-bit DRAM capacitor cell having a design rule of deep-sub-half-micron, it is known in the art that a capacitance of at least
30
femto Farad (fF) needs to be ensured.
In an attempt to fabricate capacitors of high capacitance on a semiconductor substrate at an acceptably limited area, there was proposed a method where hemispherical grains (HSG) are grown in a stacked or cylindrical structure.
FIGS. 1
a
to
1
c
are drawings illustrating a method for fabricating semiconductor capacitors according to the prior art, which show the mechanism of hemispherical grain (HSG) growth.
The hemispherical grain (HSG) growth mechanism will now be described. As shown in
FIG. 1
, amorphous silicon nuclei
12
are first deposited on the surface of a polycrystalline silicon layer
10
of a substrate (not shown). As shown in
FIG. 1
b
, the surface of the resulting structure is then subjected to a thermal treatment process
20
, so that polycrystalline silicon atoms are diffused and crystallized with respect to the deposited silicon nuclei
12
. As shown in
FIG. 1
c
, the crystallization of the polycrystalline silicon is further accelerated to achieve the hemispherical grain (HSG) growth. Thus, the surface of the polycrystalline silicon is changed into a hemispherical shape, so that the polycrystalline silicon has an increased surface area per unit area. In this way, the capacitance of the capacitors is maintained at constant level, even in the case of a highly integrated semiconductor device.
However, the gap between the capacitors, which are applied in a current 64M-DRAM fabrication process, is about 0.17 &mgr;m. In this case, if the polycrystalline silicon nuclei are deposited and the amorphous silicon is crystallized to achieve the hemispherical grain growth, a margin for the gap between the capacitors will be further reduced. Thus, the bridge and contact between the capacitors are generated. In addition, many costs are incurred during the process of the hemispherical grain (HSG) growth, thereby increasing the cost of fabrication.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for fabricating semiconductor capacitors, by which the generation of the bridge and contact between the capacitors can be prevented and the increase in. fabrication costs can be prevented, and at the same time, the effective surface area of the capacitors can be increased.
To achieve the above object, the present invention provides a method for fabricating semiconductor capacitors, which comprises the steps of: forming a cylinder type polycrystalline silicon pattern on a semiconductor substrate; forming an amorphous metal film on the substrate in such a manner that the amorphous metal film covers the polycrystalline silicon pattern; crystallizing the amorphous metal film so as to form metal grains and grain boundaries; firstly etching the crystallized metal film by a wet etching process in such a manner that the polycrystalline silicon pattern is selectively exposed due to the difference in the wet etching rate between the metal grains and the grain boundaries; secondly etching the exposed portion of the polycrystalline silicon pattern by a wet etching process so as to form a storage node electrode whose surface has hemispherical grooves; and successively forming a dielectric layer and a plate electrode on the resulting structure in such a manner that they cover the storage node electrode.
In the first wet etching step, a mixed solution of H
3
PO
4
, HNO
3
and CH
3
COOH is preferably used for a wet etching solution.
In the second wet etching step, a mixed solution of HF, HNO
3
and CH
3
COOH is preferably used for a wet etching solution. Furthermore, the second wet etching step is preferably carried out according to an isotropic etching process.
Preferably, the method of the present invention further comprises the step of removing the metal film remaining after the first wet etching step, after carrying out the second wet etching step. Moreover, the step of removing the remaining metal film is preferably carried out according to a wet etching process. In this case, a mixed solution of H
3
PO
4
, HNO
3
and CH
3
COOH is preferably used for a wet etching solution.
REFERENCES:
patent: 5877063 (1999-03-01), Gilchrist
patent: 6146966 (2000-11-01), Hirota et al.
patent: 6194266 (2001-02-01), Chen et al.
patent: 6211010 (2001-04-01), Lee et al.
patent: 6333227 (2001-12-01), Kim et al.
patent: 6492243 (2002-12-01), Reinberg
patent: 315780 (2000-11-01), None
Lee Dong Ho
Park Jong Woon
Hynix / Semiconductor Inc.
Norton Nadine
Tran Binh X.
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