Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-03-25
2004-04-27
Tran, Minh-Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S344000, C257S345000, C257S387000, C257S389000, C257S409000
Reexamination Certificate
active
06727568
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-52924, filed on Aug. 30, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, the present invention relates to a semiconductor device having a trench region for isolation and a local oxidation of silicon(LOCOS) region for reducing leakage current, and to a method of fabricating the same.
BACKGROUND OF THE INVENTION
In a semiconductor device, leakage current results in faulty operation of the semiconductor device. The leakage current includes a gate induced drain leakage(GIDL) current. The GIDL current is generated in a drain region overlapped with a gate electrode.
FIG. 1
illustrates a plan view of a conventional semiconductor device.
FIG. 2
illustrates a cross-sectional view taken along an I-I′ line of FIG.
1
. Referring to
FIGS. 1 and 2
, in a general semiconductor device, an isolation layer
102
is formed at a predetermined region of a semiconductor substrate
100
to define an active region
104
. A gate electrode
124
crosses over the active region
104
. A gate oxide layer
122
is interposed between the gate electrode
124
and the active region
104
. A shallow channel diffusion layer
106
is formed in the active region
104
under the gate oxide layer
122
. A source region
130
and a drain region
132
are present in the active region
104
adjacent to the channel diffusion layer
106
. The source region
130
and the drain region
132
have a region ‘A’ overlapped with the gate electrode
124
.
FIG. 3
illustrates a diagram indicating the ‘A’ region of
FIG. 2
to illustrate a GIDL current in a semiconductor device. Referring to
FIG. 3
, the GIDL current is generated by a band-to-band tunneling resulting from a high electric field which is induced between the gate electrode
124
and the drain region
132
. Thus, electron-hole pairs are generated, so that carriers flow out toward the semiconductor substrate
100
having a relatively lower potential than the drain region
132
.
The leakage current also includes a subthreshold leakage current meaning that a current flows via the substrate under the gate electrode. As a result, a transistor is turned on at a lower voltage than an operation voltage.
FIG. 4
illustrates a cross-sectional view taken along a II-II′ line of
FIG. 1
illustrating a subthreshold leakage current of a semiconductor device. Referring to
FIG. 4
, when a shallow trench isolation technology is applied, the gate oxide layer
122
becomes thin at the boundary B between the active region
104
and the isolation layer
102
, and this may result in an inverse narrow width effect. Thus, the transistor is turned on at a lower gate voltage than the operation voltage, and thus, a subthreshold leakage current flows via the substrate under the gate electrode
124
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a structure capable of preventing a GIDL current, and a method of fabricating the same.
It is another object of the present invention to provide a semiconductor device having a structure reducing a subthreshold leakage current flowing in a boundary of an active region near an isolation layer, and a method of fabricating the same.
It is still another object of the present invention to provide a semiconductor device showing a superior operation characteristic at a high operation voltage, and a method of fabricating the same.
The present invention is directed to a semiconductor device having a thick oxide pattern under an edge of a gate electrode. The semiconductor device includes a trench isolation layer that is formed at a predetermined region of a semiconductor substrate to define an active region. A gate electrode is arranged to cross over the active region. First and second conductive regions are formed in the active regions of both sides of the gate electrode overlapped with the edges of the gate electrode. An oxide pattern is interposed at least between the edges of the gate electrode and each of the first and second conductive regions. A gate oxide layer is interposed between the active region and the gate electrode. The oxide pattern is thicker than the gate oxide layer.
Each of the first and second conductive regions can include a heavy doped diffusion layer and a lightly doped diffusion layer. The heavy doped diffusion layer may be formed at the top of the lightly doped diffusion layer. The heavy doped diffusion layer may be formed in the active region apart from the oxide pattern, or in the active region contacting the oxide pattern. The oxide pattern may be interposed between the gate electrode and each of the first and second conductive regions. The both ends of the oxide pattern may be extended to the bottom of the gate electrode to cover the boundary between the isolation layer and the active region. That is, the oxide pattern may have a closed loop shape.
The present invention is directed to a method of fabricating a semiconductor device. In the method, a thick oxide pattern is formed at a region where a gate electrode and a drain are overlapped. In order to realize this, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in the active region. The preliminary lightly doped diffusion layers cross over the active region in parallel with each other. Oxide patterns are formed to cover each top of the preliminary lightly doped diffusion layers and to define a channel region at a predetermined portion of the active region. A gate oxide layer is formed on the channel region. Then, a gate electrode, whose edge is overlapped with the oxide pattern, is formed to cover the entire surface of the gate oxide layer and to cross over the active region. Impurities are implanted in the active region using the gate electrode as an ion-implantation mask, to form a lightly doped diffusion layer including the preliminary lightly doped diffusion layer, and to form a heavy doped diffusion layer which is shallower than the lightly doped diffusion layer, at the top of the lightly doped diffusion layer. The oxide pattern is thicker than the gate oxide layer.
REFERENCES:
patent: 6413823 (2002-07-01), Wu et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tran Minh-Loan
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