Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-05
2004-05-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S357000, C257S360000, C257S361000, C257S546000, C257S786000, C361S019000, C361S054000, C361S056000, C361S111000, C361S091100, C361S091200, C361S091500
Reexamination Certificate
active
06734504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrostatic discharge protection of integrated circuit devices, and more particularly, to an electrostatic discharge protection device that is decoupled from an integrated circuit device.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuit devices such as common silicon integrated circuits typically have delicate construction that is susceptible to damage by voltage spikes such as voltage spikes caused by electrostatic discharge. Such voltage spikes may occur in various situations such as during manufacturing of an integrated circuit, handling of the integrated circuit after packaging, and handling of a board after assembly such as during use of the board. There are a number of models that may be used to describe such damage to an integrated circuit device. For example, the human body model (HBM) describes a voltage spike condition caused by electrostatic discharge from a human body to an integrated circuit device. For an integrated circuit device to be commercially viable, it has to be protected against this condition except under special circumstances such as when manufacturers and customers specifically agree on the lack of such protection. This agreed upon lack of HBM protection is necessary because lack of this protection may require special handling of the integrated circuit device that complicates logistics, increases handling costs, and increases the probability of damaging the device.
To protect against electrostatic discharge, a silicon die typically includes protection circuitry (or an “HBM structure”) that will divert or otherwise dissipate the energy caused by a voltage spike. In this manner, the core logic circuitry of the die may not be damaged by the voltage spike. An HBM structure is the “first line of defense” for input/output (I/O) cells. Therefore, the structure is integrated into the die and is adjacent to or outside of the I/O cells through which the die interacts with the external environment (i.e., through device pins).
Development of the HBM structure, however, is usually difficult as development hinges upon understanding of process technology and how its various underlying factors interact so that an adequate structure can be developed. An adequate HBM structure also has to react fast to a voltage spike (i.e., it has to react faster than the internal circuitry) to be effective. In addition, HBM structures have to dissipate relatively large amounts of energy. On the other hand, an HBM structure cannot present an undue burden to I/O cells in areas such as current consumption and capacitance as these factors affect the performance of the device.
There are several disadvantages of currently available HBM structures. For example, the electrical design of an HBM structure is difficult to develop correctly without some experimentation due to lack of means of accurate simulations. In particular, the electrical design of an HBM structure may be difficult to develop if a new process is being used for the die. In addition, the practice of integrating an HBM structure into the base die, where the logic and regular I/O circuitry reside, may cause revision of the entire die if the HBM structure is inadequately designed. Such revision may be especially problematic if the revision of the die is solely required due to the HBM structure because the expensive tape-out of the die adds no value to the performance or functionality of the device. Additionally, while an optimal HBM structure is desired for a device, the fact that its revision causes expensive revision of the entire die and re-tape-out discourages experimentation of HBM structures thereby hindering HBM structure design. Furthermore, an HBM structure may enlarge the size of the integrated circuit die thereby increasing die cost and making a die revision for any reason more expensive than it would be without the HBM structure. Revision of an HBM structure if an existing one is inadequate requires re-layout of the device that often goes beyond the structure itself. For example, such revision may affect the I/O cell layout of the device. This revision and/or re-layout may delay product launch and increase the product development time and cost.
Accordingly, it may be advantageous to develop an HBM structure that allows revision of the HBM structure without revision of the entire die and/or re-tape-out or re-layout of the entire device, allows less problematic and less expensive revision such that better HBM structures may be developed, reduces the size of the die thereby reducing cost of the die and revision of the die for any reason, reduces product development time and costs, and allows reuse of the HBM structure for various integrated circuits.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by an embodiment of a semiconductor device including an integrated circuit and an HBM structure formed on separate semiconductor substrates. Various embodiments described herein may reduce, and even eliminate, problems such as HBM structure-induced integrated circuit latch-up, integrated circuit partitioning problems due to the HBM structure, and product delay due to HBM structure development. In addition, if an integrated circuit and an HBM structure are formed on different semiconductor substrates, then the die size of the integrated circuit may be reduced thereby reducing integrated circuit manufacturing costs. There are several additional advantages to the various embodiments as described herein.
In an embodiment, the integrated circuit may be formed on a first semiconductor substrate. The HBM structure may be formed on a second semiconductor substrate. The integrated circuit may include, for example, logic circuitry, charged-device model (CDM) structures, other circuitry typically included in an application specific integrated circuit (ASIC), and optionally portions of the input/output cells of the integrated circuit. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit. In an embodiment, the HBM structure may also include input/output cells of the integrated circuit. The input or output or input/output circuitry may be included in the input/output cells. The HBM structure may also include protection structures coupled to the input or output or input/output circuitry. The semiconductor device may also include a package substrate to which the first and second semiconductor substrates may be connected directly or through a pair of back to back diodes. The protection structures of the HBM structure may be further coupled to signal traces of the package substrate. In this manner, the protection structures may be configured to protect the input/output cells of the integrated circuit from electrostatic discharge that may be conducted through the signal traces.
In an embodiment, the input or output or input/output circuitry of the HBM structure may be coupled to the integrated circuit by wire bonding. In an alternative embodiment, the input or output or input/output circuitry of the HBM structure and the integrated circuit may be coupled to a signal trace within the package substrate by wire bonding. In a further embodiment, the input or output or input/output circuitry of the HBM structure and the integrated circuit may be connected to a signal trace within the package substrate by solder bumps. According to yet another embodiment, the semiconductor device may also include two or more HBM structures. Each of the two or more HBM structures may include a portion of the input or output or input/output circuitry and protection structures coupled to the portion of the input or output or input/output circuitry.
Latch-up and other problems associated with the HBM structure may be reduced, and even eliminated, by an HBM structure de-coupled from the integrated circuit. For example, when the HBM structure is integrated into the integrated circ
Chen Yue
Lie James H.
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Huynh Andy
Nelms David
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