Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-06
2004-07-27
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S487000
Reexamination Certificate
active
06768170
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more specifically relates to a superjunction type power MOSFET with increased avalanche energy.
BACKGROUND OF THE INVENTION
Superjunction power MOSFETs are well known. The static and dynamic characteristics of such devices are also described in “Analysis of the Effect of Charge Imbalance on the Static and dynamic Characteristics of the Superjunction MOSFET by Proveen M. Shenoy, Anup Bhalla and Gray M. Dolay, Proceeding of the ISPSD '99, pp. 99-102, June 1999.
In such devices, the avalanche capability, sometimes called “ruggedness” is determined mainly by the means of preventing the turn on of the inherent parasitic bipolar transistor in a DMOS type MOSgated device. However, in the superjunction device, the concentration of the P type columns is chosen to maintain charge balance in the active area of the epitaxial silicon body material. This requirement lowers the avalanche capability of the device because the high field locates in the N type region of the epitaxial silicon layer, resulting in a higher base resistance R
b
1
in the avalanche current path through the N type region and to the N+ source. Thus, in some designs, avalanche energy, that is, the amount of energy which is produced in avalanche without failure, has been as low as 50 millijoules. Attempts to increase this energy results in a reduction of the device breakdown voltage.
It would be desirable to increase the avalanche energy of a superjunction device without degrading the breakdown voltage.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, the P column dose in a superjunction device is increased to a value intentionally higher than that required for charge balance in apparent disregard of the accepted theory and design rules for superjunction devices. By doing so, the high field location moves from the N region to the P column, and, therefore, a lower R
b
1
or lateral base resistance is experienced by the avalanche current through the P column to the source. Thus, the avalanche capability of the device is significantly improved (by a factor greater than 10) without degrading breakdown voltage.
For example, in a prior design using an N epi layer concentration of 1.26E15 and a P column dose of about 1E13, the P column dose was increased to 1.1E13 and avalanche energy was increased from 50 millijoules to 2500 millijoules. The P column dose to be used is dependent on die size and it was found that a higher dose can be used on smaller area die. Thus, a P column dose of 1.2E13 was used for a die of size 110×140 mils; while a dose of 1.1E13 was used on larger die of 257×330 mils and 315×450 mils. In all cases, a dose of 1.1E13 to 1.3E13 can be used to improve avalanche capability without adversely affecting breakdown voltage.
REFERENCES:
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patent: 4587712 (1986-05-01), Baliga
patent: 5766966 (1998-06-01), Ng
patent: 6040600 (2000-03-01), Uenishi et al.
patent: 6140679 (2000-10-01), Ferla et al.
Simulated Superior Performances of Semiconductor Superjuction Devices, Tatsuhiko Fujihira and Yasushi Miyasaka, Proceedings of 1998 Intellectual Symposium on Power Semiconductor Devices & ICS, Kyoto.
Analysis of the Effect of Charge Imbalance on the Static and Dynamic Characteristics of the Super Junction Mosfet, Praveen M. Shenoy, Anup Ghalla and Gary M. Dolny, pp. 99-102, 1999 IEEE.
International Rectifier Corporation
Lewis Monica
Ostrolenk Faber Gerb & Soffen, LLP
Wilczewski Mary
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