Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-09-10
2004-07-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S677000, C438S622000, C438S618000, C438S253000, C438S240000, C438S238000, C438S243000, C438S246000, C438S629000, C438S656000, C438S637000, C438S303000, C257S379000, C257S754000, C257S640000, C257S635000
Reexamination Certificate
active
06759333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method.
2. Related Background Art
Dual damascene process has been used as a technique for making contact holes and interconnections in DRAM-type semiconductor and NAND-type semiconductor storage devices (such as NAND-type flash memory).
FIGS. 4A and 4B
are plan views show in a part of bit line interconnections of a DRAM product and NAND product both made by using conventional dual damascene process. Circles drawn by broken lines in
FIGS. 4A and 4B
indicate contact regions C where contact holes in the cell area are formed.
In general, contact regions C of DRAM are not juxtaposed to each other but located to be close to neighboring interconnections as shown in FIG.
4
A. In contrast, contact regions C in the memory cell area of NAND product are juxtaposed as shown in FIG.
4
B.
As shown in
FIGS. 4A and 4B
, each contact region C bulges out toward adjacent interconnections or adjacent contact regions of adjacent interconnections, making the distance between adjacent interconnections in locations of the contact regions very narrows. Therefore, there is a high possibility of short-circuiting between adjacent interconnections. In the NAND product having juxtaposed contact regions C, the possibility of short-circuiting between adjacent interconnections is especially high around the contact regions.
FIG. 5
is a cross-sectional view of the semiconductor device shown in
FIG. 4A
, taken along the X—X line of FIG.
4
A. The silicon substrate
10
includes element-isolating portions
20
and doped silicon regions
30
in its top surface region. A silicon nitride film
40
and a silicon oxide film
50
are formed to overlie the top surface of the silicon substrate
10
. Contact holes
60
are formed to penetrate the silicon nitride film
40
and the silicon oxide film
50
, and the contact holes
60
are filled with doped polycrystalline silicon
70
. Furthermore, interconnections
2
made up of two kinds of metal layers
80
,
90
are formed to overlie the doped polycrystalline silicon
70
and to embed the silicon oxide film
50
.
As shown in
FIG. 5
, in conventional semiconductor devices, width L
1
of the interconnection
2
in each contact region C is larger than the diameter R of the contact hole
60
, and this results in decreasing the line-to-line distance S beside the contact region C. A reason why the width L
1
becomes larger than the diameter R lies in the conventional semiconductor device manufacturing method. To clarify this problem, the conventional method for manufacturing a semiconductor device is explained below.
FIGS. 6A through 6J
are cross-sectional views of the conventional semiconductor device manufacturing method in the order of its processes.
In
FIG. 6A
, trench capacitors, impurity diffusion layers, gate interconnection layers (all not shown) and isolations
20
are already formed in a silicon substrate
10
. In this process, a silicon nitride film
40
and a silicon oxide film
50
are deposited and planerized as a layer-to-layer insulating film on the top surface of the silicon substrate
10
.
In
FIG. 6B
, the silicon oxide film
50
and the silicon nitride film
40
are next removed selectively by photolithography technique and dry etching to create contact holes
60
of bit lines in the cell area of DRAM.
In
FIG. 6C
, the structure next undergoes processing by hydrofluoric acid to remove the naturally oxidized films on bottoms of the contact holes
60
. This hydrofluoric acid processing is named the first hydrofluoric acid processing herein below.
In
FIG. 6D
, the doped polycrystalline silicon
70
doped with an N-type impurity is next deposited by LP-CVD, and thereafter selectively removed from the top surface of the silicon oxide layer
50
and partly from inside the contact holes
60
.
In
FIG. 6E
, contact holes
61
are next formed in the peripheral circuit area by photolithography technique and dry etching.
In
FIG. 6F
, a coat film
91
is applied to prevent from reflection in the later photolithographic process, and in
FIG. 6G
, the coat film
91
and the silicon oxide film
50
are selectively removed by photolithography technique and dry etching to create bit line interconnection trenches
92
. In
FIG. 6H
, the photo resist
93
and the coat film
91
are removed.
In
FIG. 6I
, the structure next undergoes hydrofluoric acid processing for the purpose of removing the naturally oxidized film from the exposed part of the silicon substrate
10
and from the top surface of the doped polycrystalline silicon
70
. This hydrofluoric acid processing is named the second hydrofluoric acid processing herein below.
In
FIG. 6J
, titanium
94
is next deposited by sputtering and annealed in an N
2
atmosphere. Thereby, titanium silicide is formed on the bottom of the contact, holes
61
in the peripheral circuit area and on top surfaces of the doped silicon
70
in the cell area. Titanium
94
on the parts other than the bottoms of the contact holes
61
and the top surfaces of the doped polycrystalline silicon
70
is nitrified. After that, tungsten is deposited, and it is partly removed together with the titanium nitride from the top surf ace of the silicon oxide film
50
by CMP, thereby to obtain the semiconductor device having the structure shown in FIG.
5
.
In this conventional manufacturing, process, the diameter of each contact hole
60
is enlarged by the first hydrofluoric acid processing as shown in FIG.
6
C. Additionally, the upper part of each contact hole
60
above the doped silicon
70
is further enlarged in diameter by the second hydrofluoric acid processing as shown in FIG.
6
I.
Due to this second hydrofluoric acid processing, width L
1
of the interconnection
2
becomes wider than the diameter R of the contact hole
60
. As a result, as shown in
FIG. 4A
, the line-to-line distance S of bit lines in the memory cell area inevitably decreases.
A countermeasure against this problem might be to start with a smaller diameter of the contact hole
60
(
FIG. 6B
) and a smaller width of the bit line interconnection (FIG.
6
G). However, in DRAM products, the pitch of the bit line interconnections in the cell area is determined according to the minimum design rule acceptable for photolithography technique in order to minimize the area of the memory cell area. Therefore, it is difficult to further decrease the photo resist space size. Also, for decreasing the diameter of the opening pattern of the photo resist in the process of forming the contact hole
60
, there is a limit in view of the capability of photolithography technique. Furthermore, even if the diameter of the opening pattern of the photo resist can be decreased in the process of forming the contact hole
60
, it may lead the problem of undesirable increase of the contact resistance.
These problems are similarly involved in other products (for example, NAND products as shown in
FIG. 4B
) that are similar to DRAM products in structure.
As such, it is desirable to provide a semiconductor device and its manufacturing method capable of preventing undesirable short-circuiting between interconnections by securing a wider distance between adjacent interconnections beside each contact region than the conventional one.
SUMMARY OF THE INVENTION
A semiconductor device according to an embodiment of the invention comprises: a first conductor formed inside or on the top surface of a semiconductor substrate; an insulating film formed on the top surface of said semiconductor substrate or on the top surface of said first conductor; contact holes penetrating said insulating layer to reach said first conductor; a second conductor filled inside said contact holes and electrically connected to said first conductor; and an interconnection extending across contact regions on a top surface region of said insulating layer where said contact holes are formed respectively, and having opposite sides at least one of which is in contact with said second conductor inside said contac
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Yevsikov Victor V
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