Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-12
2004-07-27
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S613000, C438S612000, C228S180220
Reexamination Certificate
active
06767819
ABSTRACT:
BACKGROUND OF THE INVENTION
This patent application is related to a co-pending patent application Ser. No. 09/952,337 (attorney reference number 3003.000800/DC10179) entitled “Semiconductor Device With Compliant Electrical Terminals, Apparatus Including The Semiconductor Device, and Methods for Forming Same” by Michael A. Lutz and filed on the same day as the present patent application.
1. Field of the Invention
This invention relates generally to electrical apparatus having terminals, and, more particularly, to electrical apparatus having area array terminals for forming electrical connections.
2. Description of the Related Art
During manufacture of an integrated circuit, signal lines that are formed upon a silicon substrate and which are to be ultimately connected to external devices, are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit (i.e., chip) is typically secured within a protective semiconductor device package. Each I/O pad of the integrated circuit is then connected to one or more electrical terminals of the device package.
The electrical terminals of a device package are typically arranged either about a periphery of the package, or in a two-dimensional array across an underside surface of the package. Metal conductors are typically used to connect the I/O pads of the integrated circuit to the terminals of the device package. The metal conductors may be, for example, fine metal bond wires, “traces” (i.e., signal lines) formed on and/or within a substrate of the device package, traces formed on and/or within a flexible carrier film or laminate such as a tape automated bonding or TAB tape, or a lead frame. Peripheral terminal device packages may have, for example, terminals called “pins” for insertion into holes in a printed circuit board (PCB), or terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a PCB. Area array terminal device packages typically have solder “balls” or “bumps” for attachment to flat metal pads on an exposed surface of a PCB.
Area array terminal packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of area array terminal packages having hundreds of terminals are much smaller than their peripheral terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from integrated circuit I/O pads to device package terminals are shorter, thus the high frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral terminal device packages.
Controlled collapse chip connection (C
4
) is a well known method of attaching an integrated circuit directly to a substrate (e.g., fiberglass-epoxy printed circuit board material or a ceramic substrate). The C
4
attachment method is commonly referred to as the “flip chip” attachment method. In preparation for C
4
attachment, the I/O pads of the integrated circuit are typically arranged in a two-dimensional array upon an underside surface of the integrated circuit, and a corresponding set of bonding pads are formed upon an upper surface of the substrate. A solder “bump” is formed upon each of the I/O pads of the integrated circuit. For example, several layers of constituent metals of a solder alloy may be deposited on the I/O pads of the integrated circuit. Following deposition of the metal layers, the integrated circuit may be heated to melt the metal layers. The molten metals may mix together to form the solder alloy, and the surface tension of the solder alloy may cause the molten solder alloy to form hemispherical solder “bumps” on the I/O pads of the integrated circuit. Solder paste is typically deposited upon each of the bonding pads of the substrate.
During C
4
attachment of the integrated circuit to the substrate, the solder bumps on the I/O pads of the integrated circuit are placed in physical contact with the solder paste on the corresponding bonding pads of the substrate. The substrate and the integrated circuit are then heated long enough for the solder to melt or “reflow.” When the solder cools, the I/O pads of the integrated circuit are electrically and mechanically coupled to the bonding pads of the substrate.
A popular type of area array terminal device package is the “flip chip” ball grid array (BGA) device package. A typical “flip chip” BGA device package includes an integrated circuit mounted upon an upper surface of a larger package substrate using the C
4
or “flip chip” attachment method described above. The substrate includes two sets of bonding pads: a first set arranged on the upper surface adjacent to the integrated circuit, and a second set arranged in a two-dimensional array across an underside surface of the BGA device package. One or more layers of electrically conductive traces (i.e., signal lines) formed on and/or within the substrate connect respective members of the first and second sets of bonding pads. Members of the second set of bonding pads function as device package terminals. A solder ball is attached to each member of the second set of bonding pads. The solder balls allow the BGA device package to be surface mounted to an ordinary PCB.
A problem arises in that the coefficients of thermal expansion (CTEs) of the integrated circuit and the package substrate typically differ. This difference in CTEs creates mechanical stresses within the solder bumps during the solder reflow operation described above. Further, following attachment of the integrated circuit to the package substrate, the integrated circuit heats up while dissipating electrical power during operation, and cools down when not operating. Again, the difference in the CTEs of the integrated circuit and the package substrate creates mechanical stresses within the solder bumps during the resultant thermal cycling. Left unchecked, these mechanical stresses typically cause the solder bump connections to fatigue and fail after an unacceptably small number of thermal cycles.
A common solution to the above described CTE mismatch problem is to form a layer of an underfill material in the region between the integrated circuit and the substrate during a final portion of the “flip chip” attachment process. The underfill material encapsulates the C
4
connections and mechanically “locks” the chip to the substrate, reducing mechanical stresses in the solder bump connections during thermal cycling, thereby significantly increasing the reliabilities of the solder bump connections.
A problem arises in that rework of such underfilled integrated circuit device packages is very difficult. In addition, the underfill process is time consuming, and constitutes a process the semiconductor device manufacturing industry would like to eliminate.
The present invention is directed to compliant electrical terminals which may be used to achieve highly reliable electrical connections despite CTE mismatches (e.g., between integrated circuits and package substrates), and without the required use of an underfill material.
SUMMARY OF THE INVENTION
An apparatus is disclosed including an electrical conductor and an electrically conductive, compliant bump formed on the electrical conductor. The compliant bump includes an electrically conductive, solderable capping layer and an electrically conductive, compliant body positioned between the solderable capping layer and the electrical conductor. In general, the solderable capping layer may be broadly described as “solder wettable.” In particular, the solderable capping layer may include one or more of the following metals: lead, tin, cadmium, indium, bismuth, gallium, copper, silver, platinum, palladium, and nickel. The compliant body electrically couples the solderable capping layer to the electrical conductor.
The electrical conductor may be, for example, an input/o
Dow Corning Corporation
Williams Morgan & Amerson
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