Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-12
2004-07-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06760893
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally related to integrated circuits (ICs) and, more particularly, to using transition times on signal lines in an IC to determine whether the signal lines have potential noise problems associated with them.
BACKGROUND OF THE INVENTION
As the geometries in integrated circuits (ICs) become ever increasingly smaller, the metallic signal lines on the ICs have become smaller in width and the spacing between the signal lines has decreased. This decrease in the width of the signal lines has increased the resistance of the signal lines. In order to reduce the resistance of the signal lines, the signal lines have been increased in height. However, this increase in height coupled with the reduction in the spacing between the signal lines increases the capacitance between adjacent signal lines. A given signal line has a signal line on each side of it, which results in the line in question coupling charge onto the lines on each side of it. Because the spacing between the lines is becoming smaller, the coupling capacitance between the lines is increasing. In addition, charge is also coupled onto the lines by elements on the IC above and below the signal lines.
This capacitance creates concerns because if, for example, the lines on both sides of the line in question are transitioning from high to low, and the line in question is at a high level, the coupling capacitance between the lines can cause the line in question to dip down to some extent below its high level. If the voltage level on the line in question dips down far enough, then the logic gate that is connected to the line in question sees a transition to a low level, which results in an erroneous state.
Various scenarios exist that make such an erroneous transition a concern. In one scenario, if the erroneous transition occurs simultaneously with, or very close in time to the end of the clock period, then the register that is capturing the next state will receive an erroneous state. Another scenario is, if the line in question is transitioning from low to high as the line on either side of it is transitioning low, the transition speed of the line in question will be reduced. If the transition speed is sufficiently reduced, then the timing requirements of the register downstream will not be met, i.e., the setup time of the downstream register will be violated. The setup time is the amount of time before the clock transitions that the data needs to be valid at the input to the register. In another scenario, if the adjacent lines are transitioning in the same direction as the line in question, then the transition speed of the line in question will be increased, which can cause hold time requirements to be violated. The hold time is the amount of time after the clock transitions that the voltage level (i.e., high or low) on the line must remain valid before it changes.
Accordingly, a need exists to be able to determine whether such transitions will result in noise on signal lines that is sufficient to cause setup and/or hold time requirements to be violated or to cause erroneous data to be latched in a register.
SUMMARY OF THE INVENTION
In accordance with the present invention, maximum transition time constraints for drivers of different sizes driving signal lines of respective maximum lengths are compared to signal transition times of an IC design to determine whether a potential noise problem exists with respect to the signal lines. Each driver size has a maximum line length constraint and a corresponding maximum transition time constraint associated with it. These maximum transition time constraints are used to determine whether the signal lines connected to respective drivers in the IC will have potential noise problems associated with them.
In accordance with the preferred embodiment of the present invention, each signal line is checked for potential noise problems. For each signal line in the IC design, the signal transition time is determined and compared to the maximum transition time constraint associated with the size of the driver driving the signal line. If the signal transition time exceeds the maximum transition time constraint, a potential noise problem exists with respect to the signal line.
These and other features and advantages of the present invention will become apparent from the following description, drawings and claims.
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Agilent Technologie,s Inc.
Dimyan Magid Y.
Siek Vuthe
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