Semiconductor memory device having a main word-line layer...

Details Semiconductor memory device having a main word-line layer... Semiconductor memory device having a main word-line layer...

2003-05-29

2004-07-20

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S226000, C365S230060, C365S230030

Reexamination Certificate

active

06765815

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a multilevel interconnection structure.
2. Description of the Related Art
Hitherto, this kind of semiconductor memory device includes a DRAM in which a memory chip is divided into banks, each bank is divided into subblocks, and then, each subblock has a plurality of memory mats arranged in a matrix form. In the DRAM with the above structure, sense amplifier (SA) areas are arranged along two opposite sides of each memory mat, at least one sub-word driver (SWD) area is disposed along another or two other opposite sides thereof. It is assumed that the SA areas are arranged on both sides of each memory mat in parallel to word lines (namely, in the X direction) and the SWD areas are arranged so as to intersect the X direction. In other words, the SWD areas are arranged in the Y direction in parallel to each other and the SA areas are arranged in the X direction in parallel to each other. Column selection lines YS extend in the Y direction.
To meet the demands of large scale integration, the following attempt is being made in the above-mentioned DRAM: Circuits for controlling or driving sense amplifier circuits and sub-word driver circuits are arranged in intersection areas (hereinbelow referred to as crossing areas) of the SA areas and the SWD areas because the crossing areas are not used as the SA areas and the SWD areas. Accordingly, the crossing areas can be used effectively. The arrangement of the SWD areas and the effective use of the crossing areas result in the high-speed operation of the DRAM.
Further, according to recent trends, in order to respond to requests to reduce the size of a chip, various lines are arranged not only between the adjacent memory mats but also over the memory mats. For example, lines including power lines, local input/output lines LIO, main input/output lines MIO, and signal lines are arranged on different layers so as to form a mesh pattern (hereinbelow referred to as a mesh arrangement). The mesh arrangement is becoming more widely used.
As this type of semiconductor memory device, for example, Japanese Unexamined Patent Publication (JP-A) No. 2002-15578 (hereinbelow, referred to as a first cited document) discloses a DRAM. For the array structure of the DRAM, a divided word driver (DWD) system is used and a hierarchical structure (multilevel interconnection) is used. In other words, input/output lines such as local I/O lines LIO, global input/output lines GIO, and similar lines are arranged on different layers. In addition, the first cited document includes an arrangement in which a sub-amplifier or a CMOS switch is disposed in a crossing area.
The multilevel interconnection on each of the memory mats of the DRAM disclosed in the first cited document will now be specifically described. As shown in
FIG. 8
contained in the first cited document, the multilevel interconnection on the memory mat include word lines, bit lines, and capacitors. The word lines are integrated with the gate electrodes of respective MOSFETs formed in a substrate. The bit lines are formed above the word lines, with an insulating film therebetween. The bit lines are connected to a diffusion layer. The bit lines are formed in a first metal layer (hereinbelow, referred to as an M
1
layer). The capacitors are connected to the diffusion layer. The capacitors are arranged above the bit lines. The capacitors are connected to a plate electrode. In this case, the M
1
layer includes a polysilicon layer FG serving as a first layer and sub-word lines SWL.
A second metal layer (hereinbelow, referred to as an M
2
layer) including main word lines MWL is arranged on the plate electrode. A third metal layer serving as a top layer (hereinbelow, referred to as an M
3
layer) is further arranged on the M
2
layer. The M
3
layer includes column selection lines YS. The multilevel interconnection structure is formed as mentioned above. In the M
3
layer, the column selection lines YS extend in the Y direction, namely, parallel to columns. In the M
2
layer, the main word lines MWL extend parallel to rows so as to intersect the Y direction, namely, in the X direction.
On the other hand, the multilevel interconnection in each of sub-word driver (SWD) areas will now be described. The SWD areas each have a sub-word driver included in peripheral circuits surrounding the memory mat. This multilevel interconnection comprises the M
2
layer and the M
3
layer. The M
2
layer includes the main word lines MWL, X-direction signal lines (arranged parallel to the word lines), and meshed power lines. These lines are arranged in the X direction. The M
3
layer includes sub-word-selection signal lines FXT and FXB to select a word line, power lines used in the SWD area, power lines used for circuits in the adjacent crossing area, and main I/O lines MIO. These lines are arranged in the Y direction.
As mentioned above, the first cited document discloses the following structure: In the memory mats and the SWD areas for the peripheral circuits, the main word lines MWL are arranged in the X direction in the M
2
layer under the M
3
layer. On the other hand, the column selection lines YS and the sub-word-selection signal lines FXT and FXB are arranged in the Y direction in the M
3
layer on the M
2
layer. The lines YS and the lines FXT and FXB are needed for the memory mats and the SWD areas.
It turns out that when the main word lines MWL are arranged in the X direction in the M
2
layer over the memory mats and the SWD areas, the arrangement of the lines in the SWD areas is limited. Specifically speaking, it is necessary to arrange the sub-word-selection signal lines FXT and FXB to select a word line and the power lines in each SWD area. The lines FXT and FXB and the power lines have to be electrically connected to the sub-word lines SWL arranged in the M
1
layer.
In the multilevel interconnection structure in which the sub-word-selection signal lines FXT and FXB and the power lines are arranged in the M
3
layer (top layer), therefore, it is necessary to electrically connect the sub-word-selection signal lines FXT and FXB and the power lines in the M
3
layer to the sub-word lines SWL in the M
1
layer through the M
2
layer in the SWD area. In addition, it is necessary to electrically connect the sub-word-selection signal lines FXT and FXB and the power lines in the M
3
layer to the diffusion layer and the gates under the M
1
layer. In this instance, it is necessary to consider that the number of sub-word-selection signal lines FXT and FXB is larger than the number of main word lines MWL and the number of lines FXT and FXB is also larger than the number of sub-word lines SWL.
Accordingly, in the M
2
layer, it is necessary to form a pattern of islands for connecting the lines FXT and FXB in the M
3
layer to the lines SWL in the M
1
layer. It is also necessary to arrange the lines for connection in the SWD area in the M
2
layer. In other words, in the M
2
layer in the SWD area, it is necessary to form islands for electrically connecting the lines FXT and FXB to the M
1
layer in addition to the lines MWL, the X-direction signal lines, and the meshed power lines. In this case, the following technique is used in the SWD area: In the M
2
layer, the lines MWL, the X-direction signal lines, and the meshed power lines are arranged so as to avoid the islands connected to the lines FXT and FXB. Accordingly, in the multilevel interconnection structure disclosed in the first cited document, the number of lines other than the lines MWL in the M
2
layer is limited by the islands formed in the M
2
layer and the lines for connection in the SWD area.
The following are considered to be the disadvantages of the above-mentioned conventional array interconnection structure: As the integration density of the DRAM becomes higher in the future, the size of each array will become larger and the number of circuits arranged in each crossing area wil

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