Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-31
2004-04-27
Chen, Jack (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S637000, C438S299000, C438S595000
Reexamination Certificate
active
06727543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates to a semiconductor structure. More particularly, this present invention relates to a memory structure and the method for manufacturing the same.
2. Description of the Prior Art
With the increasing integration of semiconductor structure, the technology of forming an embedded memory structure, such as an embedded dynamic random access memory (embedded DRAM), is more and more important. However, the formation of the spacers in an embedded memory structure is a challenge in the manufacturing of the above-mentioned structure. The requirement of the scale of the spacers is different for the memory device and for the periphery device. In the case of the embedded DRAM, based on the element requirement, such as the implanting requirement, the spacer of the logic device must be a bigger one. On the other hand, the spacer of the DRAM is a smaller one, and the following process, such as the contact formation, will not be affected by the spacer of the DRAM.
Hence, in order to improve the efficiency of the embedded memory structure, it is an important object to provide an embedded memory structure with the spacers in required scale for the periphery device and the memory device, and the method for manufacturing the above-mentioned embedded memory structure.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating a memory structure so that the spacers of the periphery device and the memory device in the above-mentioned embedded memory structure can be formed in required scale respectively.
It is another object of this invention to disclose a memory structure with the spacers in the required scale for the periphery device and the memory device in the memory structure, and thus the spacers in the embedded memory structure can attach the requirement of the semiconductor manufacture.
In accordance with the above-mentioned objects, the invention discloses a memory structure and the method for manufacturing the same. According to this prevent invention, at least a first gate structure and at least a second gate structure are provided on a substrate. After an implanting process, the first gate structure will become a periphery device, and the second gate structure will become a memory device of an embedded memory structure. A first spacer is formed on the sidewall of the first gate structure and the sidewall of the second gate structure. Next, a second spacer is formed on the sidewall of the first gate structure and the sidewall of the second gate structure. After the formation of the contact between the memory devices, the second spacer on the sidewall of the second gate structure is removed. As a result of the above-mentioned steps, an embedded memory structure with spacers in different scale is formed thereby. The spacer on the sidewall of the first gate structure comprises the first spacer and the second spacer. The spacer on the sidewall of the second gate structure only comprises the first spacer. Therefore, it is notably that an embedded memory structure with spacers in required scale for the periphery device and the memory device can be formed thereby, and following process will not be affected by the spacers in the embedded memory structure.
REFERENCES:
patent: 6165857 (2000-12-01), Yeh et al.
patent: 6306760 (2001-10-01), Hsu et al.
Chen Jack
Hyunh Yennhu B.
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