Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-03
2004-07-13
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S197000, C438S238000, C438S254000, C438S151000, C438S152000, C438S166000
Reexamination Certificate
active
06762444
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device and a technology for manufacturing the same, and particularly to a technology effective for application to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).
BACKGROUND OF THE INVENTION
An SRAM has been used as a cache memory used for a personal computer and a work station.
The SRAM comprises a flip-flop circuit for storing one-bit information therein and two information transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors). The flip-flop circuit comprises, for example, a pair of drive MISFETs and a pair of load MISFETs.
A problem associated with a soft error produced due to an &agr; ray arises in each memory cell of such a memory. The soft error produced due to the &agr; ray is a phenomenon in which an &agr; ray contained in external cosmic radiation, or an &agr; ray emitted from a radioactive atom contained in a package material for an LSI enters a memory cell and damages or corrupts information stored in the memory cell.
In order to take measures against such an &agr; ray, a method has been discussed which adds a capacitor or capacitance to an information storage unit (corresponding to an input/output part of the flip-flop circuit) in the memory cell to thereby increase the capacitance of the information storage unit. The capacitance of such an information storage unit has been described in, for example, IEDM 1998, P205.
SUMMARY OF THE INVENTION
With recent high integration and scale-down of a semiconductor integrated circuit in particular, there is a tendency to reduce the area of each memory cell. As a result, information storage units, i.e., a pair of drive n channel type MISFETs and a pair of load p channel type MISFETs are reduced in distance therebetween and susceptible to an &agr; ray. There is a tendency to reduce a source voltage (Vcc) for the purpose of a reduction in power consumption. Thus, the rate of occurrence of the soft error due to the &agr; ray rises.
On the other hand, a so-called system LSI (Large Scale Integrated Circuit) has been discussed in which the above SRAM and, for example, a PLL (Phase Locked Loop) circuit or the like having an analog capacitor are formed on a single substrate.
As the analog capacitor used in the PLL circuit, for example, a capacitor is used wherein a semiconductor substrate (diffused layer) is used as a lower electrode, a gate insulating film formed on the semiconductor substrate is used as a capacitive insulating film, and a conductive film (e.g., polysilicon film) on the gate insulating film is used as an upper electrode.
However, a tunnel current occurs in such a capacitor with thinning of the gate insulating film. As a result, a leak current increases. Subsequently to a 0.13-&mgr;m generation, for example, one exceeding 1×10
−4
A/cm
2
indicative of a target value of the leak current appears, thus inhibiting the normal operation of the PLL circuit.
When the capacitor is formed on the semiconductor substrate, it is affected by a substrate potential and a voltage characteristic of the capacitor will vary.
An object of the present invention is to provide a semiconductor integrated circuit device, e.g., a high-performance semiconductor integrated circuit device which reduces a soft error produced in each memory cell of an SRAM.
Another object of the present invention is to improve the performance of a semiconductor integrated circuit device, e.g., a system LSI wherein an SRAM and a device having an analog capacitor are formed on a single substrate.
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
(1) A semiconductor integrated circuit device according to the present invention has a pair of conductive layers which electrically connects gate electrodes and drains of a pair of n channel type MISEETs constituting each of memory cells, a capacitive insulating film formed on the pair of conductive layers and having an opening provided on any one of the pair of conductive layers, and an upper electrode formed on the capacitive insulating film and the opening. The pair of conductive layers may be formed in the interlayer insulating film. Further, upper portions of the conductive layers may protrude from the surface of the interlayer insulating film. An area for forming the upper electrode may be formed wider than an area for forming each conductive layer, and the upper electrode may be formed so as to contain the conductive layer forming area.
(2) There is provided a second area in addition to a first area in which the memory cell is formed. The second area may be formed with other capacitors respectively formed in the same layer as the conductive layers, capacitive insulating film and upper electrode formed in the first area.
(3) A method of manufacturing a semiconductor integrated circuit device, according to the present invention includes a step of defining wiring trenches in an interlayer insulating film on a pair of n channel type MISFETs constituting each of memory cells, and embedding a conductive film therein to thereby form a pair of conducive layers which electrically connects gate electrodes and drains of the pair of n channel type MISFETs, a step of forming a capacitive insulating film over the pair of conductive layers, a step of selectively removing the capacitive insulating film on any one of the pair of conductive layers to thereby define an opening, and a step of depositing a conductive film on the capacitive insulating film including the interior of the opening and etching it to thereby form an upper electrode. After the formation of the pair of conductive layers, the surface of the interlayer insulating film may be etched so as to expose side walls of the pair of conductive layers. A second area is provided in addition to a first area formed with the memory cell. Other capacitor may be formed in the second area in the same step as the step of forming each of the pair of conductive layers, capacitive insulating film and upper electrode.
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F. Ootsuka, M. Nakamuira, T. Miyake, S. Iwahashi, Y. Ohira, T. Tamaru, K. Kikushima and K. Yamaguchi, “A Novel 0.20 &mgr;m Full CMOS SRAM Cell Using Stacked Cross Couple with Enhanced Soft Error Immunity”, 1998 IEEE, IEDM 98-205, pp. 98 205 to 98-208-.
Kazama Hideto
Nonaka Yusuke
Omori Sohei
Ootsuka Fumio
Shimamoto Satoshi
A. Marquez, Esq. Juan Carlos
Fischer, Esq. Stanley P.
Luu Chuong Anh
Reed Smith LLP
Renesas Technology Corporation
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