Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-08-27
2004-04-20
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06725414
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to memory modules, and particularly to methods and apparatus for implementing error correcting code separate from the memory circuits in memory modules.
BACKGROUND OF THE INVENTION
Systems for storing and recalling information have been developed over the years in conjunction with the advances in computing technology. One of the primary considerations in architecting these memory systems is the ability to accurately read the incoming information and reproduce it correctly when writing it out again. Such electronically-represented information is comprised of a series of bits, each bit having a total of two possible states. It is recognized that a change in the value of a single bit can greatly affect the outcome of a mathematical operation or the meaning of the recorded information. Completely error-free transmission is as-of-yet unattainable. Data errors introduced during transmission, however, can be greatly reduced by the use of parity bits. Simply described, additional bits are added to the string of data bits in a predetermined pattern such that if an error is later introduced the error is detectable and often able to be corrected by logic at the receiving end. One of the better-known codes employed to provide such an error management system developed by R. W. Hamming and is referred to as Hamming code. In its simplest form a message is divided into fixed-length blocks of bits where some of the bits are data bits and the rest of the bits are check bits which are set according to the Hamming code pattern. The ratio of data bits to check bits is such that in any one block any double-bit error can be detected and all single-bit errors are corrected.
There is a cost associated with the described error management process. The standard method of implementing such error correcting code in memories is to incorporate error correction code in the memory circuitry. This type of implementation results in a reduction in amount of memory available for data because of the increased overhead necessary to manage the check bits. For example, each thirty-two bit data word requires an additional seven bits to hold the verification code, necessitating a thirty-nine bit wide memory. Thus the commonly-used thirty-six bit wide single in-line memory module (SIMM) is not available to be used, although this is a conventional and popular size SIMM. In addition, SIMMS are typically created using memory modules that are four, eight, nine, sixteen, or eighteen bits wide. As a result the amount of memory required must be selected as multiples of these sizes. This may require extra memory space to store differently configured memory. This phenomenon was noted by Stanley Wolf, Ph.D. in
Silicon Processing for the VLSI Era
(1990). Wolf noted that the addition of parity bits imposed a memory area penalty, requiring up to 27% more memory cells to store the same amount of data.
Different approaches have been taken to address this limitation. One known method is to provide the additional space for the check bits, and accept the increased cost in non-standard SIMMS and reduced amount of area available for memory as a trade-off for reliable data. Other methods add circuitry to the memory device itself. An example of this method is shown in U.S. Pat. No. 5,481,552, entitled “Method and Structure for Providing Error Correction Code for 8-byte Data Words on SIMM Cards”, and issued to Aldereguia et al. Aldereguia discloses a method of associating a system of latches with a memory such that the check bits for each data word are stored separately from the data bits. The system described by Aldereguia allows the conventional 36-bit SIMMS to be used, but doubles the number of memory reads or writes for each data access. U.S. Pat. No. 4,926,426, issued to Scheuneman et al. and entitled “Error Correction Check During Write Cycles”, discloses another method of incorporating error correction code in memory devices. Scheuneman describes coupling an error checking and correction circuit with the output means within a dynamic random access memory such that errors may be detected during the read and write cycles. Both of these applications place additional circuitry within the already crowded memory device itself. There remains a need for an error correction system which does not impinge on the valuable real estate of a memory device and which has minimal impact on the speed of memory accesses.
SUMMARY OF THE INVENTION
The present invention teaches a method and apparatus for providing reliable communication between a processor and memory devices. What is provided is a memory module comprising a plurality of independently addressable memory devices, a communication path for bi-directional data communication between the driver unit and an external processor, and error correction circuitry electrically located between the driver unit and the communication path. According to one embodiment a driver unit is connected to the plurality of independently addressable memory devices and control signal inputs. In another embodiment the error correction circuitry is incorporated into the driver unit.
In one embodiment the memory module includes a circuit board to which the memory devices are affixed. Another embodiment of the present invention comprises a processor and a memory module comprising error correction circuitry. In a further embodiment the error correction circuitry detects errors in communications between the memory module and an external processor. In another embodiment the error correction circuitry corrects errors in communications between the memory module and an external processor.
According to one embodiment of the invention the plurality of memory devices comprise dynamic random access memories (DRAMs). In another embodiment the plurality of memory devices comprise static random access memories (SRAMs). One embodiment provides memories which are directly mounted on the printed circuit board and environmentally encapsulated. Another embodiment provides memories which are wire-bonded to a lead frame and then encapsulated in plastic, the packaged memory devices then being electrically connected to the circuit board.
Another feature provided by the present invention is chip yield enhancement. In one embodiment of the present invention, the memory devices are sorted before they are included in the memory module, such that there is zero correlation of failing bits among the memories in any one memory module. Also provided is a method of populating a memory module, the memory module having a plurality of independently addressable memory devices and error detection circuitry. The method comprises the steps of testing individual memories to determine locations of defective cells, selecting a plurality of the individual memories such that there is no coincidence of the locations of defective cells among the selected plurality of individual memories, and mounting the selected plurality of individual memories on the memory module such that the error detection circuitry is electrically located between the plurality of memories and an external processor. By this method and system less-than-perfect memory devices are productively used rather than having to be discarded.
A method of error-free communication with a memory module is also provided, the memory module comprising a plurality of independently addressable memories and error correction circuitry. This method comprises the steps of transmitting a write request message to a memory module from a processor, the message information comprising blocks of bit strings, receiving the message at the memory module, modifying the message by appending check bits to each of the blocks of bits, and multiplexing the modified message to the memories. Further steps of this method comprise a memory module receiving a read request from a processor, demultiplexing the requested message from the plurality of independently addressable memories, using the appended check bits to verify the requested message and to correct the message if an e
Baker Stephen M.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Error correction chip for memory applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Error correction chip for memory applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction chip for memory applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3196764