Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-04
2004-04-27
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S774000, C257S775000
Reexamination Certificate
active
06727538
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a method and structure for improved alignment tolerance in multiple, singularized plugs.
BACKGROUND OF THE INVENTION
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer memory.
Interconnecting and completing the millions of microscopic components typically entails forming contact plugs, covering the plugs and components with an insulative layer of silicon dioxide, and then etching narrow, but often deep, holes in the insulative layer to expose portions of the components, or contact plugs underneath. These holes are then filled with another conductive material, or are developed into additional component parts, e.g., storage nodes for memory cells.
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), is one example of an electrical component requiring contact plugs and etched holes for connection to other portions of an integrated circuit. IGFET's are frequently used in both logic and memory chip applications. An IGFET uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel. Plug contacts and contact openings are required in IGFETs to complete the conductance circuit between the source and drain regions.
Current industry demands are pushing toward increased capacity on individual semiconductor chips in order to yield greater functionality. The push for increased circuit density has been realized through an increase in the miniaturization of individual components, the number of surface layers, and in the depth of contact openings between individual surface layers. Unfortunately, while design rules have shrunk, the registration of layers, or alignment of contacts from one surface layer to the next, has not improved at the same aggressive rate. The problem is compounded by the fact that the very deep contact openings include some taper to them which reduces the alignment tolerance even more dramatically.
Thus a continual need exists for creating improved contact structures, including the formation of contact plugs and contact openings, to improve the registration between semiconductor layers.
SUMMARY OF THE INVENTION
The above mentioned problems with registration tolerances between layers and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A method and structure are provided which accord improved results.
In particular, an illustrative embodiment of the present invention includes an integrated circuit device on a substrate. The device includes a number of semiconductor surface structures which are spaced apart along the substrate. A number of plugs contact to the substrate between the number of surface structures. The number of plugs includes an inner plug and a pair of outer plugs. Each one of the outer pair is formed adjacent to and on opposing sides of the inner plug. Each one of the outer pair has an upper portion which covers areas of the surface structures. An inner electrical contact couples to the inner plug and is separated from the upper portions of the outer plugs by spacers.
In another embodiment, a memory device is provided. The memory device includes multiple insulated wordlines with top surfaces. The insulated wordlines are spaced apart from one another and formed on a substrate. A bitline plug is located between an adjacent pair of the insulated wordlines. The bitline plug has a top surface beneath the top surfaces of the adjacent pair. A pair of storage node plugs are located on the opposite side of the adjacent pair of insulated wordlines from the bitline plug. The pair of storage node plugs each have a top surface above the top surfaces of the insulated wordlines and are formed over portions of the adjacent wordlines. A buried bitline couples to the bitline plug. And, a pair of opposing spacers are located above the adjacent pair of insulated wordlines such that the spacers isolate the buried bitline from the pair of storage node plugs.
In another embodiment, a data handling system is provided. The data handling system includes a central processing unit and a memory device which are coupled together by a system bus. The memory device includes the memory device discussed above.
Another embodiment of the present invention includes a method of forming plugs between multiple semiconductor surface structures on a substrate. The method includes forming a first opening in a first isolation layer on the semiconductor surface structures. Forming the first opening includes exposing portions of the substrate between the multiple surface structures. A first conductive material is deposited in the first opening to cover the multiple surface structures. A second isolation layer is formed across the first conductive material. A second opening is formed in the first conductive material in a source region on the substrate. Forming the second opening includes exposing portions of an adjacent pair of the multiple surface structures. The method further includes forming spacers on interior walls of the second opening. Forming the spacers includes separating the first conductive material into an inner plug, isolated beneath and between the adjacent pair, and a pair of outer plugs. The outer plugs also cover portions of the adjacent pair. Further, a second conductive material is formed in the second opening and is isolated from the outer plugs by the spacers.
Thus, a method and structure for an improved alignment tolerance between semiconductor layers are provided. The invention discloses a novel method for forming individual contact plugs with an increased surface area for improved registration tolerance to contact openings having a taper.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Thomas Toniae M.
Zarabian Amir
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