Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
2000-10-04
2004-01-20
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C710S048000, C712S244000, C714S034000, C714S035000
Reexamination Certificate
active
06681280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to interrupt control apparatus and methods, particularly to interrupt control apparatus having a break-interrupt function of interrupting execution of a program in a so-called debugger, i.e., a system for supporting debug of a program.
2. Description of the Related Art
Conventionally, high-performance processors have been used in the fields of supercomputers, general-purpose computers, and workstations. In addition, recently, high-performance processors are also used in the field of built-in devices because the required processing capability increases. Such a processor has an interrupt processing function. When an interrupt occurs, the processor performs interrupt processing in accordance with an instruction of an interrupt handler, which is an interrupt processing program.
When a processor is used in the field of supercomputers, general-purpose computers, or workstations, the interrupt handler is generally provided as part of the system program. Contrastingly when a processor is used in the field of built-in devices, the user often generates his own interrupt handler as part of an application program. Hence, when this interrupt handler is generated, not only the application program but also the interrupt handler itself is subjected to debug.
A processor has various interrupt functions such as an instruction breakpoint, a data breakpoint, a software breakpoint, and step execution as effective functions of supporting debug of a program. Interrupts by the instruction breakpoint, data breakpoint, software breakpoint, and step execution will be totally called a “break-interrupt”, and an interrupt other than the break-interrupt will be called a “normal interrupt”, thereby discriminating them from each other.
An interrupt by an instruction breakpoint occurs when the address (instruction break address) of an instruction to be interrupted is set in a register, and the instruction break address set in this register matches the instruction address of an actually executed instruction. An interrupt by a data breakpoint occurs when the address (data break address) of data to be interrupted is set in a register, and the data break address set in this register matches the address of data accessed in accordance with a load instruction or store instruction.
An interrupt by a software breakpoint occurs when a breakpoint instruction for generating an interrupt is inserted to an arbitrary position in a program, and the breakpoint instruction is executed when the program is being sequentially executed in accordance with the progress of a program counter. An interrupt by step execution occurs every time one instruction of a program is executed.
By using the above-described break-interrupt function, execution of a program is interrupted to confirm repeatedly calculation results stored in a register or memory, thereby debugging the program.
FIG. 1
is a representation showing an example of state transition when a processor interrupt occurs.
Referring to
FIG. 1
, reference numeral
301
denotes a user state (normal operative state without any interrupt) of the processor; and
302
denotes a supervisor state (privilege instruction execution state by an interrupt) of the processor. When the processor is processing a normal application, the state of the processor is the user state
301
. When an interrupt
303
, i.e., a break-interrupt or normal interrupt occurs in the user state
301
, the processor transits to the supervisor state
302
. When an interrupt return instruction
304
is executed in this supervisor state
302
, the processor returns to the user state
301
.
FIG. 2
is a representation showing another example of state transition when a processor interrupt occurs.
Referring to
FIG. 2
, reference numeral
311
denotes a user state of the processor; and
312
,
313
, and
314
denote supervisor states of the processor. When the processor is processing a normal application, the state of the processor is the user state
311
. When an interrupt
315
, i.e., a break-interrupt or normal interrupt occurs in the user state
311
, the processor transits to the supervisor state
312
.
When an interrupt return instruction
316
is executed in the supervisor state
312
, the processor returns to the user state
311
. However, when an interrupt
317
, i.e., a break-interrupt or normal interrupt occurs in the supervisor state
312
before execution of the interrupt return instruction
316
, the processor transits to another supervisor state
313
. When an interrupt return instruction
318
is executed in the supervisor state
313
, the processor returns to the previous supervisor state
312
.
Interrupt processing control will be described below with reference to
FIG. 2
by exemplifying processor state transition: user state
311
→supervisor state
312
→user state
311
due to an interrupt.
When the interrupt
315
, i.e., a break-interrupt or normal interrupt occurs in the user state
311
, the processor writes, in a register, information on program counter value, processor state, and factor of the interrupt at the time of interrupt, thereby saving the processor operation information before the interrupt. The processor transits to the supervisor state
312
and shifts processing from the application program to an interrupt handler.
Immediately after the shift to processing of the interrupt handler, i.e., immediately after the interrupt processing, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is inhibited, thereby inhibiting a new interrupt. When the interrupt processing progresses to some extent, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is permitted, thereby permitting a new interrupt (e.g., the interrupt
317
).
When processing of the interrupt handler is almost ended, and the interrupt return instruction
316
is executed in the supervisor state
312
, the processor returns to the user state
311
before the interrupt. At this time, the processor operation information before the interrupt is restored on the basis of the information on program counter value and processor state which are written in the register before the interrupt, thereby returning the processor to the user state
311
before the interrupt.
Immediately before this interrupt return as well, write in the register is inhibited, thereby inhibiting a new interrupt. When interrupt return of the processor is ended, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is permitted, thereby permitting a new interrupt.
As described above, in the conventional interrupt control apparatus, when an interrupt occurs, a write in the register used to write the processor operation information is inhibited immediately after the interrupt operation and immediately before interrupt return. For this reason, interrupt inhibition periods when a new interrupt is inhibited are present immediately after the interrupt operation and immediately before interrupt return. In addition, the processor writes the processing operation information before the interrupt in the same register without discriminating a break-interrupt from a normal interrupt. Hence, immediately after a normal interrupt occurs or immediately before its return, no break-interrupt can occur because of the presence of interrupt inhibition periods. For this reason, the interrupt handler cannot be completely debugged.
Many conventional debug support systems have a break-interrupt function of interrupting execution of a program to verify the operation of the program. The break-interrupt function occasionally stops execution of a program at an arbitrary position designated in advance in the program to be debugged. This function is effective for program debug processing and incorporated in many debug support systems.
This break-interrupt function can be implemented by various sche
Miyake Hideo
Nakamura Yasuki
Suga Atsuhiro
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