Magnetic random access memory

Details Magnetic random access memory Magnetic random access memory

2002-06-27

2004-09-21

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

06795334

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-390670, filed Dec. 21, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) which stores “1”- and “0”-data using a magnetoresistive effect.
2. Description of the Related Art
In recent years, many memories which store data by new principles have been proposed. One of them is a magnetic random access memory which stores “1”- and “0”-data using a tunneling magnetoresistive (to be referred to as TMR hereinafter) effect.
As a proposal for a magnetic random access memory, for example, Roy Scheuerlein et al, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, p. 128 is known.
A magnetic random access memory stores “1”- and “0”-data using TMR elements. As the basic structure of a TMR element, an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, various kinds of TMR element structures have been proposed to, e.g., optimize the MR (MagnetoResistive) ratio.
Data stored in the TMR element is determined on the basis of whether the magnetizing states of the two magnetic layers are parallel or antiparallel. “Parallel” means that the two magnetic layers have the same magnetizing direction. “Antiparallel” means that the two magnetic layers have opposite magnetizing directions.
Normally, one (fixed layer) of the two magnetic layers has an antiferromagnetic layer. The antiferromagnetic layer serves as a member for fixing the magnetizing direction of the fixed layer. In fact, data (“1” or “0”) stored in the TMR element is determined by the magnetizing direction of the other (free layer) of the two magnetic layers.
When the magnetizing states in the TMR element are parallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the TMR element is minimized. For example, this state is defined as a “1”-state. When the magnetizing states in the TMR element are antiparallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the TMR element is maximized. For example, this state is defined as a “0”-state.
Currently, various kinds of cell array structures have been examined for a magnetic random access memory from the viewpoint of increasing the memory capacity or stabilizing write/read operation.
For example, currently, a cell array structure in which one memory cell is formed from one MOS transistor and one TMR element (or an MTJ (Magnetic Tunnel Junction) element) is known. Additionally, a magnetic random access memory which has such a cell array structure and stores 1-bit data using two memory cell arrays so as to realize stable read operation is also known.
However, in these magnetic random access memories, it is difficult to increase the memory capacity. This is because one MOS transistor corresponds to one TMR element in these cell array structures.
BRIEF SUMMARY OF THE INVENTION
(1) According to a first aspect of the present invention, there is provided a magnetic random access memory comprising: a plurality of memory cells which are stacked one another and connected in series to store data using a magnetoresistive effect; a bit line which is connected to one terminal of each of the plurality of memory cells and extends in a first direction; and a read circuit connected to the bit line.
According to a second aspect of the present invention, there is provided a magnetic random access memory comprising: a plurality of memory cells which are stacked one another and connected in parallel to store data using a magnetoresistive effect; a bit line which is connected to one terminal of each of the plurality of memory cells and extends in a first direction; and a read circuit connected to the bit line.
According to a third aspect of the present invention, there is provided a magnetic random access memory comprising: a plurality of memory cells which are stacked one another and formed by combining series connection and parallel connection to store data using a magnetoresistive effect; a bit line which is connected to one terminal of each of the plurality of memory cells and extends in a first direction; and a read circuit connected to the bit line.
(2) According to an aspect of the present invention, there is provided a manufacturing method of a magnetic random access memory, comprising: forming a read select switch on a surface region of a semiconductor substrate; forming a first write line extending in a first direction on the read select switch; forming a first MTJ element right above the first write line; forming a second write line extending in a second direction perpendicular to the first direction right above the first MTJ element; forming, right above the second write line, a second MTJ element which is symmetrical to the first MTJ element with respect to the second write line; forming a third write line extending in the first direction right above the second MTJ element; forming, right above the third write line, a third MTJ element which is symmetrical to the second MTJ element with respect to the third write line; forming a fourth write line extending in the second direction right above the third MTJ element; forming, right above the fourth write line, a fourth MTJ element which is symmetrical to the third MTJ element with respect to the fourth write line; forming a fifth write line extending in the first direction immediately on the fourth MTJ element; and forming a read bit line extending on the second direction on the fifth write line.


REFERENCES:
patent: 5748519 (1998-05-01), Tehrani et al.
patent: 5852574 (1998-12-01), Naji
patent: 5894447 (1999-04-01), Takashima
patent: 6072718 (2000-06-01), Abraham et al.
patent: 6128329 (2000-10-01), Takakusaki
patent: 6134138 (2000-10-01), Lu et al.
patent: 6169688 (2001-01-01), Noguchi
patent: 6169689 (2001-01-01), Naji
patent: 6188615 (2001-02-01), Perner et al.
patent: 2001/0035545 (2001-11-01), Schuster-Woldan et al.
patent: 2003/0198080 (2003-10-01), Iwata
patent: 1109170 (2001-06-01), None
patent: 1202284 (2002-05-01), None
patent: 1253651 (2002-10-01), None
patent: 1321941 (2003-08-01), None
patent: 11-354728 (1999-12-01), None
patent: 2001-217398 (2001-08-01), None
patent: 2001-357666 (2001-12-01), None
patent: WO 99/14760 (1999-03-01), None
patent: WO 99/18578 (1999-04-01), None
patent: WO 00/19441 (2000-04-01), None
patent: WO 00/57423 (2000-09-01), None
patent: WO 02/41321 (2002-05-01), None
R. Scheuerlein, et al., ISSCC 2000/Session 7/TD: Emerging Memory & Device Technologies/paper TA 7.2, pp. 128, 129, 409, 410 and 411, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, Feb. 8, 2000.
M. Durlam, et al., ISSCC 2000/Session 7/TD: Emerging Memory & Device Technologies/paper TA 7.2, pp. 129, 130, 131 and 95, 96 and 97, “Nonvolatile RAM Based on Magnetic Tunnel Junction Elements”, Feb. 8, 2000.
U.S. patent application Ser. No. 09/961,326, filed Sep. 25, 2001, pending.
U.S. patent application Ser. No. 10/073,339, filed Feb. 13, 2002, pending.
U.S. patent application Ser. No. 10/160,184, filed Jun. 4, 2002, pending.
U.S. patent application Ser. No. 10/162,605, filed Jun. 6, 2002, pending.
U.S. patent application Ser. No. 10/170,366, filed Jun. 14, 2002, pending.
U.S. patent application Ser. No. 10/180,024, filed Jun. 27, 2002, pending.
U.S. patent application Ser. No. 10/107,310, filed Mar. 28, 2002, pending.
U.S. patent application Ser. No. 10/160,058, filed Jun. 4, 2002, pending.
U.S. patent application Ser. No. 10/180,024, filed Jun. 27, 2002, pending.
U.S. patent application Ser. No. 10/180,517, filed Jun. 27, 2002, pending.

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