Stock material or miscellaneous articles – Structurally defined web or sheet – Including variation in thickness
Reexamination Certificate
2001-12-19
2004-07-27
Pyon, Harold (Department: 1772)
Stock material or miscellaneous articles
Structurally defined web or sheet
Including variation in thickness
C428S034100, C428S131000, C428S188000
Reexamination Certificate
active
06767614
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to a novel process for the fabrication of suspended high-aspect-ratio single crystal silicon microstructures. More particularly, the invention relates to two-, three- or more level, high-aspect-ratio, released, or suspended, single crystal silicon microstructures of complex geometries, wherein all levels are self-aligned and fabricated from a single silicon wafer, and to the isolation of or removal of selected suspended microstructures.
Interest in the fabrication of suspended microstructures has increased with the increased use of microelectromechanical systems (MEMS). Many MEMS implementations are fabricated by surface micromachining of deposited thin films, by bulk micromachining of (usually silicon) substrates, or by deep etching, as used in the Single Crystal Reactive Etching and Metallization (SCREAM) process, which is explained for example, in U.S. Pat. No. 5,198,390. As described in this patent, the SCREAM process produces a single level of suspended microstructures. Multiple level SCREAM microstructures must use multiple substrates bonded together, and most other prior techniques for fabricating multiple level structures require the assembly and alignment of numerous separately fabricated components. However, such assemblies are impractical for large arrays of micron-scale structures, and in particular for electron lenses and similar devices, where alignment is critical.
Another process for micromachining silicon substrates for fabricating microelectromechanical devices is exemplified by the process described in U.S. Pat. No. 5,501,893 to Laermer, et al. In this patent, an anisotropic plasma etching of silicon through a mask is used to provide laterally defined recesses in a substrate. The etching step is alternated with a polymerizing step which covers silicon surfaces exposed by the etching step to provide an etching stop, which prevents etching of those surfaces in a subsequent etch step. The alternating etching and protecting steps allow high anisotropy of the etched structure.
Although these processes have been successful, new technical demands have emerged for MEMS fabrication technology; in particular, the integration of MEMS with active electronics on the same chip, and the development of more complex microsystems. There is a need, therefore, for a process which will facilitate fabrication of single and multiple levels of released or suspended microstructures from a single substrate, and in particular will facilitate the fabrication of large arrays of these structures.
SUMMARY OF THE INVENTION
Briefly, the present invention is directed to improved fabrication processes for microelectromechanical structures, and to unique structures fabricated by the improved processes. In its simplest form, the invention is directed to a fabrication process which is based on both the method described, for example, in U.S. Pat. No. 5,501,893 to Laermer et al (hereafter Laermer et al) the disclosure of which is hereby incorporated herein by reference, and on the SCREAM process described, for example, in U.S. Pat. No. 5,198,390, the disclosure of which is hereby incorporated herein by reference. These processes are modified and extended and are used in such a way as to produce a combined vertical etch and release RIE process, which may be referred to herein as a “combination etch”.
Fabrication of a single-level micromechanical structure using the process of the present invention includes a novel dry etching process to shape and release suspended single crystal silicon elements, in a single dry etch step. This new process combines vertical silicon reactive ion etching (Si-RIE) and release etches to eliminate the need to deposit and pattern silicon dioxide mask layers on the sides of suspended structures, as is required in the SCREAM process. It furthermore reduces the mechanical stresses in suspended structures caused by deposited silicon dioxide films.
Briefly, the combined process includes formation of a mask structure on the surface of a silicon substrate, for example, through conventional photolithography. Thereafter, the silicon is etched through the mask using an anisotropic vertical reactive ion etching (RIE) plasma etching process using a sequence of etch and passivation cycles as described by Laermer et al. A short quasi-isotropic Si-RIE is followed by a polymerization step which conformally coats the exposed surfaces with a passivation layer. Thereafter, a second anisotropic etching step is carried out which first removes the polymer coating from the horizontal surfaces of the substrate by sputter etching, but not from the vertical surfaces, and then etches the exposed silicon quasi-isotropically. These alternating steps are repeated to produce deep structures (or trenches) having vertical edges, with the profile of the structure being determined by the balance between the passivation and etching steps.
When the desired structure depth has been reached, the structure may be released from the substrate by adjusting the length of and balance between the passivation and etching steps. A long polymerization deposits a thicker passivation layer, followed by a longer Si-RIE step which undercuts the structure to release it. This process integrates the release of suspended structures with the vertical etch that defines them, and is much simpler than prior deep etching fabrication process sequences. It allows the fabrication of delicate structures by reducing mechanical stresses in them, due to the absence of stress-inducing sidewall passivation layers and by avoiding any wet process steps which could deform the suspended structures. The process is particularly suitable for integration with active sensing devices.
In accordance with this aspect of the invention, silicon suspended structures may be produced on a single crystal silicon (SCS) substrate, or wafer, which may contain prefabricated active devices, utilizing only four steps: (1) a photolithography step which defines the layout of the suspended structures and surrounding trenches in a resist layer on the substrate; (2) a first etching step in which the pattern is transferred to the field and inter-layer dielectrics are etched in an anisotropic RIE step; (3) a second etching step in which high aspect ratio SCS suspended structures are etched and released in a single combined etch, and (4) a final step in which the photoresist is removed. The sidewall silicon dioxide film deposition and etchback utilized in prior processes such as the SCREAM process is not necessary, and no further patterning steps for interconnecting the released structure to active devices on the wafer are required, in accordance with this process. On a blank silicon wafer without dielectric films step (2) can also be skipped, reducing the number of process steps for the fabrication of suspended single crystal silicon structures to 3.
The process of the present invention further comprises an extension of the SCREAM process to allow the fabrication of multiple level structures, including but not limited to, the selective removal of parts of levels. This extension of the process enables the fabrication of suspended elements of different heights, and reduces the process-imposed restriction of previous multiple level processes that all suspended levels must have the same layout. The extended process is applied to the fabrication of novel actuators, electron lenses and micromachines, and allows multiple levels of self-aligned, suspended structures with greater design flexibility.
In the basic SCREAM process, as described in U.S. Pat. No. 5,198,390, a thick silicon dioxide film (1.5-4 &mgr;m) is placed on the surface of a substrate by thermal oxidation of the substrate or by CVD deposition. This film is patterned using a resist layer, photolithography, and CHF
3
-RIE. The silicon substrate is etched in a vertical RIE step, using the silicon dioxide and photoresist films as an etch mask. Typical etch depths range from 10 to 20 &mgr;m. A subsequent thermal oxidation or CVD deposition covers t
Adams Scott G.
Hofmann Wolfgang M. J.
MacDonald Noel C.
Neves Hercules
Hofmann Wolfgang M. J.
Jones Tullar & Cooper PC
Nordmeyer Patricia L.
Pyon Harold
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