Semiconductor memory device using ferroelectric film

Details Semiconductor memory device using ferroelectric film Semiconductor memory device using ferroelectric film

2001-09-10

2004-03-23

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S758000

Reexamination Certificate

active

06710385

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-277822, filed Sep. 13, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device using a ferroelectric film, and particularly relates to a semiconductor memory device having a highly integrated memory cell.
2. Description of the Related Art
Nowadays, a semiconductor memory is utilized in many electronic devices such as a main memory in a large-sized computer, a personal computer, home electric products, a portable telephone and the like. As kinds of semiconductors, a volatile DRAM (Dynamic RAM), a SRAM (Static RAM), a nonvolatile MROM (Mask ROM), a flash EEPROM and the like are listed.
Particularly, although DRAM is a volatile memory, DRAM is excellent in that DRAM is manufactured at low cost, the area of a cell of a DRAM is small in size as ¼ of that of a SRAM, and a high-speed operation is capable in DRAM compared with a flash EEPROM. Therefore, DRAM occupies almost all share of the market.
A rewritable nonvolatile flash EEPROM has an advantage in a point that data of the rewritable nonvolatile flash EEPROM is not erased even if the electric source is turned off. However, in the case of this flash EEPROM, the number of times of rewriting (number of times of Write/Erase) achieves only on the order of 10
6
. Besides this, there are several defaults that it takes longer, i.e., a few micro seconds to write when compared with that of a DRAM, and further, it requires a high voltage (12V to 22V) to write. Therefore, the scale of the market of flash EEPROM is not large compared with that of DRAM.
In contrast, a nonvolatile ferroelectric memory using a ferroelectric capacitor has been proposed in 1980. This ferroelectric memory is nonvolatile, besides that, this type of ferroelectric memory has advantages that the number of times of rewriting achieves as many as on the order of 10
12
, a speed of the read/write time is a high speed on the order of the speed of a DRAM and further it can be operated at 3V to 5V. Therefore, in the future, there will be a possibility that all of the memory is replaced by this ferroelectric memory, and every manufacturer carries out the development of it.
FIG. 14A
shows a general ferroelectric memory, a configuration of a memory cell consisting of one transistor and one capacitor, and a cell array. A memory cell configuring a ferroelectric memory is constituted of a cell transistor
100
and a ferroelectric capacitor
101
. These are connected in series. A cell array is constituted of bit lines BL, /BL for reading out data, word line WL
0
, WL
1
for selecting a cell transistor, plate line PL
0
, PL
1
for driving one end of the ferroelectric capacitor
101
.
However, the ferroelectric memory as shown in
FIG. 14B
is a folded bit line configuration in which one memory cell
102
is arranged at two intersections of a word line and a bit line. Therefore, suppose that each wiring width and a space between wirings is F, the minimum cell size is calculated by the formula of
2
F×
4
F=
8
F
2
.
Moreover,
FIG. 14C
shows a sectional structure of a cell array corresponding to that in FIG.
14
B.
Thus, as for a ferroelectric memory, there has been a problem that its cell size is limited to 8F
2
and the size is large the same as that of DRAM.
Moreover, as to a ferroelectric memory, it is necessary to divide a plate line for each word line and to be individually driven. This is because it prevents the destruction of electronic polarization information of a ferroelectric capacitor configuring non-select cell. Furthermore, a plurality of ferroelectric capacitors is connected to an individual plate line of a ferroelectric memory in a direction of the word line. Therefore, the load capacity of a plate line is large. In addition, it is necessary to arrange a plate line drive circuit at a pitch equal to a pitch of the word line. Therefore, it is difficult to enlarge the area for arranging a plate line drive circuit, and the size of the plate line drive circuit cannot be enlarged. Therefore, as shown in
FIG. 14D
, a delay time at the time when the potential of a plate line is raised and lowered is on the order of 30 to 100 ns, and this delay time is longer than the delay time at the time when the potential of a word line is raised and lowered. As a result, there has been a problem that the operation is delayed.
In order to solve the problem, the inventor has proposed a new ferroelectric memory which can satisfy and be compatible with three points of (1) a small, 4F
2
-sized memory cell, (2) a flat transistor which is easily manufactured, and (3) a high-speed random access function having general versatility in U.S. Pat. No. 5,903,492 and U.S. Pat. No. 6,151,242 (the contents of which are incorporated herein by reference in their entirety).
FIG. 15A
shows a configuration of a ferroelectric memory described in the related patent of the present invention described above. In
FIG. 15A
, a unit cell is constituted of a cell transistor (T) and a ferroelectric capacitor (C). The both ends of ferroelectric capacitor (C) are connected between the source and drain of the cell transistor (T), respectively. A plurality of unit cells are connected in series and configured into a memory cell block.
One end of each memory cell block is connected to bit lines BL, and /BL via a block selection transistor, the other end is connected to plate lines PL and /PL.
With this configuration, a memory cell of the minimum size of 4F
2
can be realized by using a flat transistor. At the time of standby, all the word lines WL
0
to WL
7
are made to be “H” level, and the memory cell transistor is turned on. Furthermore, block selection signals BS
0
, BS
1
are made to be “L” level, and the memory transistor is turned off. By doing so, both ends of a ferroelectric capacitor are electrically short-circuited by the cell transistor being turned on. Therefore, the potential difference is not occurred between both ends of the ferroelectric capacitor, and the memory polarization is stably maintained.
At the time of being active, only cell transistors connected in parallel to a ferroelectric capacitor from which data should be read out is turned off, and a block selection transistor is turned on. For example, in the case where the ferroelectric capacitor C
1
is selected, as shown in
FIG. 15B
, the word line WL
6
is made to be “L” level.
Subsequently, the plate line /PL at the capacitor C
1
side is made to be “H”, the block selection signal BS
0
at the capacitor C
1
side is made to be “H” level. By doing so, the potential difference between plate line /PL and bit line /BL is applied only to both ends of the ferroelectric capacitors C
1
which are connected in series to the memory cell transistor being in an OFF state. Therefore, the polarization information of the ferroelectric capacitor C
1
is read out to the bit line /BL.
Therefore, by connecting unit cells in series and selecting an arbitrary word line, cell information of an arbitrary ferroelectric capacitor can be read out, and a complete random access can be realized. Moreover, since the plate line can be shared with a plurality of unit cells, the arrangement region of a plate line can be reduced so that the size of a chip can be reduced. Therefore, there is no limitation that the pitch of the plate line drive circuit must be equal to the pitch of the word line. Therefore, the area of a plate line drive circuit (PL Driver) can be increased and a high-speed operation can be realized by increasing the drive capacity.
FIG. 16A
shows a sectional view of a part of a memory cell shown in
FIG. 15A
, and shows an example of an ideal structure. A ferroelectric capacitor having a bottom electrode BE, a ferroelectric film FE, and a top electrode TE is arranged directly above the memory cell transistor in which a word line WL serves as a gate. With

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