Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-12-20
2004-01-27
Padmanabian, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S170000, C711S171000, C711S172000, C711S201000, C711S202000, C711S212000
Reexamination Certificate
active
06684291
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interface for at least one memory, in particular a flash memory, including a plurality of memory cells combined into multiple physical sectors, in which the memory cells combined into one physical sector are capable of being erased only together, and in which the interface includes an interrogation apparatus, arrangement, or structure to interrogate (flash) memory data that encompass sector data, and an allocation apparatus, arrangement, or structure that, incorporating the sector data, allocates multiple memory cells to each logical block.
The present invention also relates to a method for providing variable configuration of a memory apparatus that includes at least one memory, in particular a flash memory, which includes a plurality of memory cells that are combined into multiple physical sectors, in which the memory cells combined into one physical sector are capable of being erased only together, where the method includes the step of reading in (flash) memory data that include sector data.
The present invention also relates to an apparatus for carrying out or performing the exemplary method of the present invention.
BACKGROUND INFORMATION
In contrast to dynamic random-access memories (DRAM), flash memories, for example, in the form of electrically erasable programmable memories (flash EEPROM) have the advantage that the data stored in them are not lost, even if the power supply is shut off. This property opens up a wide field of applications, for example, using flash memories as replacements for mechanical hard disk drives or in combination with mobile radio terminals. A flash memory may include, for example, floating gate field effect transistor components that are arranged in rows and columns. The charge stored on the floating gate of a transistor of this kind may be modified by suitable programming. The state of this charge, and thus the occupancy of the corresponding memory cell, may be sensed by scanning the corresponding voltage at the component. A line and column addressing system may be used to address a flash memory.
The structure of flash memories may make it impossible to erase individual memory cells, since only individual sectors, in which multiple memory cells are combined, may be erased. This may have a particularly strong impact on the operational behavior of flash memories because the contents of a memory cell may be overwritten only after the corresponding memory cell has been erased. For this reason, the contents of all memory cells that are occupied and are not intended to be overwritten must be stored in a sector in another region of the memory as soon as one or more memory cells in that sector need to be overwritten. It therefore may take much longer to write data into a flash memory than into a DRAM. In order to reduce the effects of this disadvantage, it is understood that write buffers may be arranged on the same IC as the flash memory itself.
In order to manage flash memories, the interface for the corresponding flash memories may allocate multiple memory cells to respective logical blocks. The interface can be provided on the same IC as the flash memory array, or separately therefrom.
Regardless of the specific configuration of the interface, in many applications it may be desirable to replace the flash memories, for example, with flash memories having a greater capacity. In such a case, a problem may arise since the interface may not be readily compatible with different flash memories, so that replacement or updating of the interface may also be necessary. To solve this problem, German Published Patent Application No. 197 82 214 relates to a component that contains a memory array, an interrogation memory, and an interface. The memory array contains a plurality of blocks of flash EEPROM memory components that are arranged so that they may be accessed in rows and columns. An interrogation memory stores data that define the characteristics of the flash memory component. The interface receives data and commands that are addressed to the flash memory component. The interface generates signals to implement the commands within the flash memory components. The interface contains a circuit for receiving a command and for answering, which is done by returning the data stored in the interrogation memory as output.
According to one embodiment referred to in German Published Patent Application No. 197 82 214, it may be possible, for example, in a computer system (e.g., a laptop), to use different flash memory components as supplements to or replacements for a hard disk drive. In this case, the interface may be located between a computer bus and the flash memory, and with the aid of the data that define the characteristics of the flash memory component, the interface may ensure that the data interchange, standardized for the particular computer bus, may be performed, irrespective of the particular flash memory component being used.
The interface of German Published Patent Application No. 197 82 214 may make it possible to use different flash memories for one specific application.
SUMMARY OF THE INVENTION
An exemplary interface according to the present invention is directed to provide an allocation of memory cells to respective logical blocks on the basis of application-specific and/or flash memory-specific block data conveyed to the interface. This block data may be modified independently of program code data. A universal interface may be used with a variety of flash memories and for different applications that require a variety of block definitions.
For this purpose, the block data may include block formation data that define which memory cells or physical sectors are allocated to which block.
Since the memory cells contained in a respective sector may only be erased all together, block formation data may be optimized so that as many block boundaries as possible of the logical blocks coincide with sector boundaries of physical sectors.
Nevertheless, one block may completely or partly include one or more physical sectors, so that logical blocks of arbitrary sizes that need not be integral multiples of sector sizes may be formed.
The block data may include block property data that may, for example, define desired utilization limitations.
In this context, the block property data may include, in particular, information as to whether and/or when a logical block or a portion of a logical block is erased and/or enabled for a write access and/or enabled for a read access, so as to for example, provide different read or write prohibitions for routines having different authorizations.
The block data may also include block linkage data that indicate memory regions to which a corresponding logical block may be linked. A logical block or several logical blocks may, for example, be linked to mirroring or protection regions of either the flash memory or another memory, depending on the application.
The flash memory data and/or the block data may be stored in one or more files. In this way, the flash memory data may be stored in one file, while the block data may be stored in another file. If the flash memory is replaced with a different flash memory, it may then be sufficient to simply replace the file that contains the flash memory data. Similarly, with the use of the two separate files, it may be sufficient to replace only the file that contains the block data, if the application changes.
The block data may be modifiable, even during operation of the interface. Since the configuration of physical sectors is predefined in accordance with the flash memory being used, it may be necessary to modify the layout of the logical blocks (i.e. the block formation data) between various revisions of a project, even, for example, within an application. It may also be necessary to modify corresponding block property data. In converting to new block data, the new block data should be compatible with the previously valid block data, so that inadvertent data loss may be prevented, for example.
In addition to the step of reading i
Kenyon & Kenyon
Padmanabian Mano
Robert & Bosch GmbH
Song Jasmine
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