Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-07-03
2004-09-21
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S798000
Reexamination Certificate
active
06794679
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device that can measure the timing difference between input and output signals.
2. Description of the Background Art
One important characteristic test of a semiconductor device is the timing measurement of measuring the time starting from a trigger input up to completion of a predetermined operation. One representative example of timing measurement is the measurement of an access time defined as starting from an issue of a read out request up to the actual appearance of output data.
In such timing measurement, the timing difference between an input signal to a semiconductor device and an output signal from the semiconductor device in response to that input signal must be measured at high accuracy. To this end, Japanese Patent Laying-Open No. 11-33167 (referred to as “conventional art” hereinafter), for example, discloses the approach to measure the timing difference between input and output signals in a unit to be tested (also called DUT “Device Unit Testing” hereinafter) at high accuracy through an external measurement apparatus.
The need arises for timing measurement to be conducted at higher accuracy in accordance with the high frequency operation of recent semiconductor devices. For example, a Double Data Rate SDRAM (referred to as DDR-SDRAM hereinafter) operating at an external operating clock of 133 MHz requires a measurement accuracy of not more than 0.1 ns for tAC defining the timing period between an external clock signal and the second subsequent output data in a burst read operation.
However, timing measurement of high accuracy using an external measurement apparatus as disclosed in the aforementioned Japanese Patent Laying-Open No. 11-133167 requires the provision of additional external measurement facility. This is because difference in the path length of a plurality of electric lines establishing connection between a DUT and a measurement apparatus must be corrected at high accuracy. In order to conduct timing measurement at high accuracy even if distortion occurs in the input and output signals caused by the crosstalk and parasitic capacitance between the plurality of electric lines, an expensive measurement apparatus of extremely high performance is required. Accordingly, the cost for measurement facility as well as the production cost will increase drastically.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device of low cost that allows measurement of timing difference between input and output signals at high accuracy.
According to an aspect of the present invention, a semiconductor device with a normal mode and a test mode as an operation mode includes an internal circuit executing a predetermined process in accordance with an input signal to provide an output signal in accordance with the predetermined process, a delay circuit delaying the input signal by respective different delay times to output n (n: natural number) delay signals in the test mode, and n comparison circuits provided corresponding to the n delay signals, respectively. Each of the n comparison circuits outputs a comparison result indicating which of a corresponding delay signal output and the output signal from the internal circuit is output earlier in said test mode.
The semiconductor device of the present invention can measure and evaluate the time required for an output signal of a predetermined process carried out by the internal circuit in response to an input signal to be output from the semiconductor device, based on a comparison result between the input signal respectively having a plurality of different delay times applied by a delay circuit and an output signal from the internal circuit. In other words, the timing difference between input and output signals can be measured in high accuracy without taking into account the adverse effect of the electrical wiling path between an external tester device and a semiconductor device that is the subject of measurement on the measurement accuracy. This eliminates the need of an expensive measurement apparatus of high performance. The increase in production cost corresponding to increase in the cost of the measurement facility can be suppressed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6333880 (2001-12-01), Mitsui
patent: 2001/0019284 (2001-09-01), Buck
patent: 2003/0116763 (2003-06-01), Yamazaki et al.
patent: 11-133167 (1999-05-01), None
McDermott Will & Emery LLP
Ngo Ngan V.
Renesas Technology Corp.
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