Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-29
2004-05-04
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S338000, C257S369000, C257S371000, C257S365000, C257S390000
Reexamination Certificate
active
06730952
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same, and more particularly, the present invention relates to a semiconductor device having improved properties and to a method of manufacturing the same in which a number of process steps is reduced by controlling ion implantation process parameters in a peripheral circuit region and a cell array region.
2. Description of the Related Art
Recently, as the use of computers in information media is expanding, rapid developments in semiconductor memory devices have also taken place. That is, highly integrated devices having improved reliability and response times have been developed, resulting in semiconductor memories with high operational speeds and large storage capacities.
Highly integrated semiconductor devices are obtained by precise electrical isolation of various elements such as transistors, diodes, resistors, and the like formed on a semiconductor substrate. Isolation parameters are adopted at an early stage of the manufacturing process and define the size of an active region and process margins of subsequent processes.
Generally, the degree of integration of semiconductor devices has exhibited a fourfold increase every three years, while the physical area of the devices has only increased 1.4 times over that same period. Thus, the pitch size between elements has been reduced. As the pitch size between elements continues to be reduced, it becomes difficult to manufacture a device having satisfactory dielectric and refresh characteristics. The process of isolating an appropriately sized portion within a limited cell array region is one of the most difficult tasks associated with achieving highly integrated semiconductor devices.
Currently, an isolation method utilizing poly spacer local oxidation is widely used for the manufacture of active patterns having small pitch sizes. However, the resulting profile becomes distorted due to the formation of a bird's beak at the side portion of the field oxide. This results in deterioration of the refresh characteristic.
To improve upon drawbacks associated with this problem, an ammonia (NH
3
) plasma process is utilized to increase the effective channel length and to compensate for the thickness of the field oxides. In this method, the growth of the bird's beak by an oxidation of the side portion of the field oxide can be restrained through nitrification of the surface portion of the field oxide by the ammonia plasma.
The nitrification reduces the oxidation of the side portion of the field oxides, thereby increasing their thicknesses. In particular, the thickness of the field oxides can be increased by about 200 Å using the ammonia plasma treatment and this increases the effective field length to about 150 Å. As such, this method advantageously results in increased process margins. However, the manufacturing process as a whole becomes more complicated.
In another method of increasing isolation, a channel stopping ion implantation is implemented under the active region. The ion implantation is carried out by applying high energy to ions and injecting the ions to penetrate the surface of a solid to be injected. Through the ion implantation, the number of impure elements and the junction depth of the active region can be correctly controlled. In addition, since the processing temperature is low, a photoresist layer can be utilized as a protection layer and the concentration of the injected impurity is almost uniform from the surface of a wafer. Further, the lateral spread of the impurity with respect to the vertical plane of the wafer surface is even less than that obtained by thermal spread.
For the silicon wafer, trivalent boron(B), pentavalent phosphor(P), arsenic(As) and the like can be utilized as the impurities. Since these elements do not have gaseous phases at ambient temperature, gaseous molecules including these impurities are utilized. BF
3
, BCl
3
, and the like can be exemplified as the molecules including boron, PH
3
can be utilized as the molecules including phosphor, and AsH
3
can be utilized as the molecules including arsenic. The ion implanting process will be schematically explained for implanting boron ions by utilizing BF
3
gas.
First, BF
3
gas molecules are introduced into a gas room so that the molecules and thermal electrons emitted from a heated filament collide. At this time, the thermions are accelerated by applying a voltage difference of about 100V to increase an ionization degree of the BF
3
gas molecules and a magnetic field is applied to increase the collision probability. From the collision of the emitted thermions and the BF
3
molecules, dissociated ions such as
10
B
+
, F
2
30
,
11
BF
+
,
11
B
+
, and the like are produced and desired,
11
B
+
ions are selected and accelerated by an appropriate magnetic field in a sorter. (The numbers preceding the letter B designate atomic weights of boron.)
After extracting the desired ions at the plasma state, a high energy is applied to accelerate the ions so that the ions impact the surface of the wafer, and the thus accelerated ions are injected into the wafer. At this time, the applied energy determines the junction depth. In order to control the concentration of the impurity, the amount of ions per unit area (atoms/cm
2
), that is, dose is controlled. The ion implanted depth is controlled by the acceleration energy (eV) of the injected ions.
One important defect in the ion implanting process is a damage imparted on the crystal lattice of a single crystal silicon wafer after the collision of the ions of high energy onto the wafer. To recover the damage and to activate the injected impurities, an annealing at about 900-1000° C. is implemented after the completion of the ion implantation process. Further, drawbacks in applying a high voltage and an introduction of poisonous gases accompany the ion implantation process. Nevertheless, the ion implantation process is commonly utilized for the formation of a P-well and N-well, for the control of a threshold voltage, and for the formation of a source/drain region.
The ion implantation process is utilized to overcome the problems caused by different processing parameters for forming a cell array region and a peripheral circuit region. For example, U.S. Pat. No. 5,576,226 (issued to Hwang) discloses a method for controlling the thickness of a gate oxide layer by selectively injecting oxidation promoting ions or oxidation retarding ions into a cell array region and a peripheral circuit region. In addition, U.S. Pat. No. 5,780,310 (issued to Koyama) discloses a method for forming a cell array region on a recess having a first impurity concentration and a peripheral circuit region having a second impurity concentration so that the cell array region is formed from a lower portion than the peripheral circuit region.
Commonly, the channel stopping ion implantation is carried out after forming the N-well/P-well and Si
3
N
4
/SiO
2
pattern. Through utilizing the Si
3
N
4
/SiO
2
pattern, B
+
ions are injected for the P-well and P
+
ions are injected for the N-well. This channel stopping ion implantation also is referred to as a field ion implantation.
Practically, the field ion implantation is separately implemented for the cell array region and the peripheral circuit region by utilizing different masks even for the same conductive type MOS regions such as NMOS or PMOS regions. The two regions have different ion implanting parameters because the thickness of a field oxide at the cell array region is about 1500 Å and that of the peripheral circuit region is about 2000 Å. Although the formation of the field oxides is carried out simultaneously for the two regions, the thicknesses of the field oxides at the two regions become different because the critical dimension at the cell array region is narrower than that at the peripheral circuit region.
Similarly, the field ion implantation processes at the NMOS cell
Tran Minhloan
Tran Tan
Volentine & Francos, PLLC
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