Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-03-14
2004-05-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S746000
Reexamination Certificate
active
06738945
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a signal transmission device and method for avoiding a transmission error, and more particularly to a signal transmission device and a method adapted to transmit an n-bit parallel digital signal for avoiding a transmission error.
BACKGROUND OF THE INVENTION
Among the integrated circuit (IC) chips, there are a larger number of data to be transmitted. Along with the increasing transmission speed, the characteristics of the transmission lines between chips critically affect the accuracy of the signal transmission. For a computer system, a central processing unit (CPU)
11
frequently accesses the digital data in a dynamic random access memory (DRAM) circuit
13
through a core logic circuit
12
as shown in FIG.
1
. Hence, the binary voltage level signal is quickly transmitted in the transmission lines between the CPU
11
and the core logic circuit
12
and between the core logic circuit
12
and the DRAM circuit
13
. However, because the equivalent capacitance value for the long transmission line is high, when the binary voltage level pulls up a data bit from “0” up to “1”, a large amount of current Id is required as shown in FIG.
2
A. On the contrary, when the binary voltage level signal pulls down a data bit from “1” to “0”, similarly a large amount of current Is is required as shown in FIG.
2
B. Therefore, when the data having many bits are transmitted by the parallel signal pattern at the same time between the core logic circuit
12
and the DRAM circuit
13
, it is possible to occur that multiple bits simultaneously generate a level changed from “0” to “1” or from “1” to “0”. The result will allow the output circuit to consume a lot of current to achieve the voltage level change. Thus, the whole system will be unstable or even result in a transmission error because the power-consumption is too big. For an 8-bit parallel digital signal, when two consecutive output data are “00000000” and “11111111”, the output voltage V will be lower than the Vdd or even lower than the threshold of the level “1”, which results in the transmission error, because the current Id as shown in
FIG. 2A
is too big. On the other hand, when two consecutive output data are “11111111” and “00000000”, the output voltage V will be higher than ground (0) or even higher than the threshold of the level “0”, which results in the transmission error, because the current Is as shown in
FIG. 2B
is also too big.
Therefore, the purpose of the present invention is to develop a device and a method to deal with the above situations encountered in the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to propose a signal transmission device adapted to transmit an n-bit parallel digital signal for avoiding a transmission error.
It is therefore another object of the present invention to propose a signal transmission device adapted to transmit an n-bit parallel digital signal for reducing power-consumption.
It is therefore an additional object of the present invention to propose a signal transmission device adapted to transmit an n-bit parallel digital signal for avoiding the system unstable.
According to the present invention, there is proposed a signal transmission device for avoiding a transmission error, adapted to transmit an n-bit parallel digital signal. The signal transmission device includes a detector, an encoder and a decoder. The detector is used for receiving a first n-bit digital data and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value representative of a bit number having level change in an n-bit, and outputting an indicating signal while the changed value is larger than a threshold. The encoder electrically connected to the detector is used for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded data of the second n-bit digital data below the threshold. The decoder electrically connected to the detector and the encoder is used for receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.
Preferably, the detector includes a delay circuit electrically connected to the encoder for delaying the first n-bit digital data outputted from the encoder in a preset time, and a Hamming distance detector electrically connected to the delay circuit for receiving the second n-bit digital data and the delayed first n-bit digital data, proceeding the first calculation to obtain a Hamming distance, and outputting the indicating signal while the Hamming distance is larger than the threshold.
Certainly, the threshold can be n/2.
Certainly, the encoder can be an exclusive-OR (XOR) operator for receiving the indicating signal and the second n-bit digital data, proceeding an exclusion operation, and outputting the encoded second n-bit digital data.
Certainly, the decoder can be an exclusive-OR (XOR) operator for receiving the indicating signal and the encoded second n-bit digital data, proceeding an exclusion operation, and recovering the second n-bit digital data.
Certainly, the encoder can be an exclusive-NOR (XNOR) operator for receiving the indicating signal and the second n-bit digital data, proceeding an exclusion-NOR operation, and outputting the encoded second n-bit digital data.
Certainly, the decoder is an exclusive-NOR (XNOR) operator for receiving the indicating signal and the encoded second n-bit digital data, proceeding an exclusion-NOR operation, and recovering the second n-bit digital data.
Preferably, the n-bit parallel digital signal is transmitted in a transmission line between two integrated circuit (IC) chips. Certainly, the two integrated circuit chips can be core logic circuit and dynamic random access memory (DRAM) circuit respectively or graphic accelerator circuit and dynamic random access memory (DRAM) circuit respectively.
According to the present invention, there is proposed a signal transmission method for avoiding a transmission error, adapted to transmit an n-bit parallel digital signal. The method includes steps of proceeding a first calculation of a first n-bit digital data and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal to obtain a changed value representative of a bit number having level change in an n-bit, outputting an indicating signal while the changed value is larger than a threshold and proceeding a second calculation to obtain an encoded second n-bit digital data for reducing the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and proceeding a third calculation of the encoded second n-bit digital data in response to the indicating signal to recover the second n-bit digital data.
Preferably, the changed value obtained by the first calculation is a Hamming distance. Preferably, the indicating signal is outputted while the changed value is larger than the threshold and the threshold is n/2.
Certainly, the second calculation can be an exclusive-OR operation of the indicating signal and the second n-bit digital data for outputting the encoded second n-bit digital data.
Certainly, the third calculation can be an exclusive-OR operation of the indicating signal and the encoded second n-bit digital data for recovering the second n-bit digital data.
Certainly, the second calculation can be an exclusive-NOR operation of the indicating signal and the second n-bit digital data for outputting the encoded second n-bit digital data.
Certainly, the third calculation can be an exclusive-NOR operation of the indicating signal and the encoded second n-bit digital data for recovering the second n-bit digital data.
According to the present invention, there is proposed a signal transmission device for avoiding a transmission error, ada
Lin Hung-Ming
Pai Hung-Ta
Chase Shelly A
De'cady Albert
Silicon Integrated System Corp.
Volpe and Koenig P.C.
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